Datasheet

Section 13 8-Bit Timers (TMR)
Rev.7.00 Mar. 18, 2009 page 666 of 1136
REJ09B0109-0700
13.5.3 Timing of Timer Output when Compare-Match Occurs
When compare match A or B occurs, the timer output changes as specified by bits OS3 to OS0 in
TCSR.
Figure 13.6 shows the timing when the output is set to toggle at compare match A.
Compare match A
signal
φ
Timer output pin
Figure 13.6 Timing of Timer Output
13.5.4 Timing of Compare Match Clear
TCNT is cleared when compare match A or B occurs, depending on the setting of the CCLR1 and
CCLR0 bits in TCR. Figure 13.7 shows the timing of this operation.
N H'00
Compare match
signal
φ
TCNT
Figure 13.7 Timing of Compare Match Clear