Datasheet

ManualsBrandsRENESAS ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller LQFP 144 (20x20) 16-Bit 34 MHz I/O number 96

Section 16 I

2

C Bus Interface 2 (IIC2) (Option)

Rev.7.00 Mar. 18, 2009 page 772 of 1136

REJ09B0109-0700

SCL

ICCRA

Transfer clock

generation

circuit

Address

comparator

Interrupt

generator

Interrupt request

Bus state

decision circuit

Arbitration

decision circuit

Noise canceler

Noise canceler

Output

control

Output

control

Transmission/

reception

control circuit

ICCRB

ICMR

ICSR

ICEIR

ICDRR

ICDRS

ICDRT

I

2

C bus control register A

I

2

C bus control register B

I

2

C mode register

I

2

C status register

I

2

C interrupt permission register

I

2

C transmission data register

I

2

C reception data register

I

2

C bus shift register

Slave address register

Legend:

ICCRA

ICCRB

ICMR

ICSR

ICIER

ICDRT

ICDRR

ICDRS

SAR

:

:

:

:

:

:

:

:

:

SAR

SDA

Internal data bus

Figure 16.1 Block Diagram of I

2

C Bus Interface 2