Datasheet

Section 16 I

C Bus Interface 2 (IIC2) (Option)

Rev.7.00 Mar. 18, 2009 page 782 of 1136

REJ09B0109-0700

16.3.5 I

C Bus Status Register (ICSR)

ICSR is an 8-bit readable/writable register that performs confirmation of interrupt request flags

and status.

Bit Bit Name Initial Value R/W Description

7 TDRE 0 R/W Transmit Data Register Empty

[Setting condition]

• When data is transferred from ICDRT to ICDRS

and ICDRT becomes empty

• When TRS has been set

• When a transition from the receive mode to the

transmit mode has been made in the slave mode

[Clearing conditions]

• When 0 is written in TDRE after reading TDRE = 1

• When data is written in ICDRT

6 TEND 0 R/W Transmit end

[Setting conditions]

• When the ninth clock of SCL is rose while the

TDRE flag is 1

[Clearing conditions]

• When 0 is written in TEND after reading TEND = 1

• When data is written in ICDRT

5 RDRF 0 R/W Receive Data Register Full

[Setting condition]

• When a received data is transferred from ICDRS

to ICDRR

[Clearing conditions]

• When 0 is written in RDRF after reading RDRF =

• When data is read from ICDRR