Datasheet

Section 16 I
2
C Bus Interface 2 (IIC2) (Option)
Rev.7.00 Mar. 18, 2009 page 788 of 1136
REJ09B0109-0700
TDRE
SCL
(master output)
SDA
(master output)
SDA
(slave output)
TEND
[5] Write data to ICDRT (third byte).
Clear TDRE.
ICDRT
ICDRS
[2] Instruction of start
condition issuance
[3] Write data to ICDRT (first byte).
Clear TDRE.
[4] Write data
to ICDRT (second byte).
Clear TDRE and TEND.
User
processing
1
Bit 7
Slave address
Address + R/W
Data 1
Data 1
Data 2
Address + R/W
Bit 6 Bit 7Bit 6Bit 5 Bit 4 Bit 3 Bit 2Bit 1Bit 0
2123456789
A
R/W
Figure 16.5 Master Transmit Mode Operation Timing 1
TDRE
[6] Issue stop condition. Clear TEND.
[7] Set slave receive mode
TEND
ICDRT
ICDRS
1923 4 56789
AA/A
SCL
(master output)
SDA
(master output)
SDA
(slave output)
Bit 7 Bit 6
Data n
Data n
Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
[5] Write data to ICDRT. Clear TDRE.
User
processing
Figure 16.6 Master Transmit Mode Operation Timing 2