Datasheet

Section 17 A/D Converter
Rev.7.00 Mar. 18, 2009 page 808 of 1136
REJ09B0109-0700
17.3 Register Description
The A/D converter has the following registers.
• A/D data register A (ADDRA)
• A/D data register B (ADDRB)
• A/D data register C (ADDRC)
• A/D data register D (ADDRD)
• A/D data register E (ADDRE)
• A/D data register F (ADDRF)
• A/D data register G (ADDRG)
• A/D data register H (ADDRH)
• A/D control/status register (ADCSR)
• A/D control register (ADCR)
17.3.1 A/D Data Registers A to H (ADDRA to ADDRH)
There are eight 16-bit read-only ADDR registers, ADDRA to ADDRH, used to store the results of
A/D conversion. The ADDR registers, which store a conversion result for each channel, are shown
in table 17.2.
The converted 10-bit data is stored to bits 15 to 6. The lower 6-bit data is always read as 0.
The data bus between the CPU and the A/D converter is 16-bit width. The data can be read
directly from the CPU.
Table 17.2 Analog Input Channels and Corresponding ADDR Registers
Analog Input Channel
Channel Set 0 (CH3 = 0) Channel Set 1 (CH3 = 1)
A/D Data Register which Stores
Conversion Result
AN0 AN8 ADDRA
AN1 AN9 ADDRB
AN2 AN10 ADDRC
AN3 AN11 ADDRD
AN4 AN12 ADDRE
AN5 AN13 ADDRF
AN6 AN14 ADDRG
AN7 AN15 ADDRH