Datasheet

Section 1 Overview
Rev.7.00 Mar. 18, 2009 page 20 of 1136
REJ09B0109-0700
Pin No.
Type Symbol
H8S/2378
0.18μm
F-ZTAT Group,
H8S/2378R
0.18μm
F-ZTAT Group
(LQFP-144)
H8S/2378
0.18μm
F-ZTAT Group,
H8S/2378R
0.18μm
F-ZTAT Group
(LGA-145)
H8S/2377
H8S/2377R
H8S/2375
H8S/2373
H8S/2375R
H8S/2373R
I/O Function
Operating
mode
control
MD2
MD1
MD0
1, 144,
143
B1, A2,
A3
1, 144,
143
1, 144,
143
Input These pins set the
operating mode.
These pins should
not be changed
while the MCU is
operating.
DCTL
*
1
62 M9 62 62 Input When this pin is
driven high for the
H8S/2378R Group,
SDRAMφ dedicated
to the synchronous
DRAM is output.
When not using the
synchronous DRAM
interface or for the
H8S/2378 Group,
drive this pin low.
The level of this pin
must not be
changed during
operation.
System
control
RES 92 F12 92 92 Input Reset pin. When
this pin is driven
low, the chip is
reset.
STBY 103 D13 103 103 Input When this pin is
driven low, a
transition is made to
hardware standby
mode.