Datasheet

Rev.6.00 Oct.28.2004 page 895 of 1016
REJ09B0138-0600H
SCKCR—System Clock Control Register H'FF3A Clock Pulse Generator
7
PSTOP
0
R/W
6
—
0
R/W
5
—
0
—/(R/W)
4
—
0
—
3
—
0
—
0
SCK0
0
R/W
2
SCK2
0
R/W
1
SCK1
0
R/W
0
1
PSTOP Normal Operation
ø output
Fixed high
High impedance
High impedance
Fixed high
Fixed high
ø Clock Output Control
Bus Master Clock Select
0
1
0
1
0
1
0
1
0
1
0
1
—
Bus master is in high-speed mode
Medium-speed clock is ø/2
Medium-speed clock is ø/4
Medium-speed clock is ø/8
Medium-speed clock is ø/16
Medium-speed clock is ø/32
—
ø output
Fixed high
Sleep Mode
Bit
Initial value
Read/Write
:
:
:
Software
Standby Mode
Hardware
Standby Mode
Reserved for
H8S/2398,
H8S/2394,
H8S/2392,
and H8S/2390.
Only 0 should
be written
to this bit.
Reserved
Only 0 should be written to
this bit.
MDCR—Mode Control Register H'FF3B MCU
7
—
1
—
6
—
0
—
5
—
0
—
4
—
0
—
3
—
0
—
0
MDS0
—*
R
2
MDS2
—*
R
1
MDS1
—*
R
Current mode pin operating mode
Bit
Initial value
Read/Write
:
:
:
Note: * Determined by pins MD
2
to MD
0
MSTPCRH — Module Stop Control Register H H'FF3C Power-Down State
MSTPCRL — Module Stop Control Register L H'FF3D Power-Down State
15
0
R/W
14
0
R/W
13
1
R/W
12
1
R/W
11
1
R/W
10
1
R/W
9
1
R/W
8
1
R/W
7
1
R/W
6
1
R/W
5
1
R/W
4
1
R/W
3
1
R/W
2
1
R/W
1
1
R/W
0
1
R/W
MSTPCRH MSTPCRL
Specifies module stop mode
0
1
Module stop mode cleared
Module stop mode set
Bit
Initial value
Read/Write
:
:
: