The revision list can be viewed directly by clicking the title page. The revision list summarizes the locations of revisions and additions. Details should always be checked by referring to the relevant text. 16 H8S/2633 Group, H8S/2633 F-ZTATTM, H8S/2633R F-ZTATTM, H8S/2695 User's Manual: Hardware Renesas 16-Bit Single-Chip Microcomputer H8S Family / H8S/2600 Series H8S/2633 HD6432633 HD64F2633 H8S/2632 HD6432632 H8S/2631 HD6432631 H8S/2633R HD64F2633R H8S/2695 HD6432695 Rev.6.00 2011.
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Notice 1. All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm the latest product information with a Renesas Electronics sales office. Also, please pay regular and careful attention to additional and different information to be disclosed by Renesas Electronics such as that disclosed through our website.
General Precautions in the Handling of MPU/MCU Products The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes on the products covered by this manual, refer to the relevant sections of the manual. If the descriptions under General Precautions in the Handling of MPU/MCU Products and in the body of the manual differ from each other, the description in the body of the manual takes precedence. 1.
Preface These LSIs are high-performance microcomputers with a 32-bit H8S/2600 CPU core and a variety of built-in peripheral functions necessary for a system configuration. The built-in peripheral devices include a 16-bit timer pulse unit (TPU), a programmable pulse 1 1 generator (PPG)* , a watchdog timer (WDT), 8-bit timers, a 14-bit PWM timer (PWM)* , serial 1 1 communication interfaces (SCI, IrDA* ), an A/D converter, a D/A converter* , and I/O ports.
H8S/2633 Group Manuals: Document Title Document No. H8S/2633 Group Hardware Manual This manual H8S/2600 Series, H8S/2000 Series Software Manual REJ09B0139 Users Manuals for Development Tools: Document Title Document No. H8S, H8/300 Series C/C++ Compiler, Assembler, Optimized Linkage Editor User's Manual REJ10J2039 H8S, H8/300 Series Simulator/Debugger User's Manual REJ10B0211 High-performance Embedded Workshop User's Manual REJ10J2169 Application Notes: Document Title Document No.
Comparison of H8S/2633, H8S/2632, H8S/2631, H8S/2633F-ZTAT, H8S/2633RF-ZTAT, and H8S/2695 Product Specifications A comparative listing of the specifications of the H8S/2633, H8S/2632, H8S/2631, H8S/2633FZTAT, H8S/2633RF-ZTAT, and H8S/2695 is provided below.
H8S/2633 Group H8S/2633F-ZTAT H8S/2633 H8S/2632 H8S/2633R Group H8S/2631 H8S/2633RF-ZTAT H8S/2695 PVCC = 4.5 V to 5.5 V Operating 25-MHz operation version voltage PVCC = 4.5 V to 5.5 V, VCC = PLLVCC = 3.0 V to 3.6 V, AVCC = 4.5 V to 5.5 V, (Single power supply version lacking VCC range Vref = 4.5 V to AVCC and PLLVCC pins) 16-MHz operation version (low-voltage version) PVCC = 3.0 V to 5.5 V, VCC = PLLVCC = 3.0 V to 3.6 V [When using A/D or D/A] AVCC = 3.6 V to 5.5 V, Vref = 3.
H8S/2633 Group H8S/2633F-ZTAT Method of fixing OSC pin when 32 kHz oscillator not used H8S/2633 H8S/2632 H8S/2633R Group H8S/2631 VCC power supply H8S/2633RF-ZTAT OSC1 OSC1 No 32 kHz oscillator. The HD6432695 is OSC2 OSC2 GND H8S/2695 Open the HD6432633. The pins corresponding to OSC1 and OSC2 in the HD64F2633 are NC pins in the HD6432695. Open Properties Output of pins 34 and 35 is normally NMOS push-pull output, but is NMOS open-drain output when the IIC bus drive function is selected.
H8S/2633 Group H8S/2633F-ZTAT 2 I C bus interface (IIC) H8S/2633 H8S/2632 Yes [option] D/A converter Yes H8S/2633R Group H8S/2631 H8S/2633RF-ZTAT H8S/2695 Yes No No Note: * The input clock frequency range is 2 to 25 MHz (2 to 16 MHz on 16-MHz operation version: H8S/2633 Group only). For 25 MHz < φ ≤ 28-MHz operation on the H8S/2633R and H8S/2695, make sure to use a PLL with a multiplying factor set to ×2 or ×4 (φ = operating frequency). Page x of lvi R01UH0166EJ0600 Rev. 6.
Notes on H8S/2695 1. Notes on P35 Pin Functions (SCK1, SCK4) in H8S/2695 The following restrictions apply to the functions of P35 (SCK1, SCK4) in the H8S/2695. The functions indicated by *2 below cannot be used in the H8S/2695, and these combinations must not be set.
2. Notes on H8S/2695 Development (Using H8S/2633 Emulator Chip) The H8S/2695 is not equipped with an I2C bus function and output from pins 34 and 35 is CMOS output (unless P34ODR or P35ODR is set to 1, respectively). These pins are used for NMOS push-pull output on the H8S/2633 emulator chip, so the output characteristics of these pins are different than is the case with the H8S/2695.
H8S/2633 Group H8S/2633F-ZTAT H8S/2633 H8S/2632 H8S/2633R Group H8S/2631 H8S/2633RF-ZTAT H8S/2695 32 kHz oscillator See section 23A, Clock Pulse Generator (H8S/2633, H8S/2632, H8S/2631, H8S/2633F) See section 23B, Clock Pulse Generator (H8S/2633R, H8S/2695) Clock Pulse Generator See section 23A, Clock Pulse Generator (H8S/2633, H8S/2632, H8S/2631, H8S/2633F) See section 23B, Clock Pulse Generator (H8S/2633R, H8S/2695) EXTAL input level See section 25, Electrical Characteristics (H8S/2633, H8S/2
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Main Revisions for This Edition Item Page Revision (See Manual for Details) 1.1 Overview 2 Table amended Table 1.1 Overview Item Specification Bus controller • Possible to connect a maximum of 8 MB of DRAM (alternatively, it is also possible to use an interval timer) External bus release function • 8 Notes: 1. Applies to the flash memory version only. 2. The FWE pin is used only in the flash memory version.
MD1 MD2 NC NC PC0/A0 PC1/A1 PC2/A2 PC3/A3 VSS PC4/A4 VCL PC5/A5 PC6/A6 PC7/A7 VSS PB0/A8/TIOCA3 PVCC PB1/A9/TIOCB3 PB2/A10/TIOCC3 PB3/A11/TIOCD3 PB4/A12/TIOCA4 PB5/A13/TIOCB4 PB6/A14/TIOCA5 PB7/A15/TIOCB5 PA0/A16 PA1/A17/TxD2 PA2/A18/RxD2 PA3/A19/SCK2 VSS P10/TIOCA0/A20 P11/TIOCB0/A21 P12/TIOCC0/TCLKA/A22 P13/TIOCD0/TCLKB/A23 P14/TIOCA1/IRQ0 NC NC P15/TIOCB1/TCLKC P16/TIOCA2/IRQ1 Page xvi of lvi 15 Vref AVCC NC NC PF0/BREQ/IRQ2 PF1/BACK PF2/WAIT/BREQO PF3/LWR/ADTRG/IRQ3 PF4/HWR PF5/RD PF6/AS VSS PF7/φ PVC
Item Page Revision (See Manual for Details) 1.3.2 Pin Functions 28 in Each Operating Mode Table amended FP-128B Mode 4 Mode 5 Mode 6 Mode 7 Table 1.2 (c) Pin Functions in Each Operating Mode (H8S/2695) 82 NC* NC* NC* NC* 30 Pin No. Pin Name Note amended Note: * NC pins should be connected to VSS or left open. . 2.6.3 Table of Instructions Classified by Function 73 Table 2.3 Instructions Classified by Function 74 R01UH0166EJ0600 Rev. 6.
Item Page Revision (See Manual for Details) 2.8.1 Overview 86 Figure amended Figure 2.14 Processing States Reset state The CPU and all on-chip supporting modules have been initialized and are stopped. Exception-handling state A transient state in which the CPU changes the normal processing flow in response to a reset, trace, interrupt, or trap instruction. 2.8.
Item Page 7.5.8 Wait Control 218 Revision (See Manual for Details) Figure amended Figure 7.18 Example Timing for Insertion of Wait States via WAIT Pin Tp Tr Program waits Tc1 Tw WAIT pin wait states Tw Tc2 φ WAIT 9.3.10 Number of DTC Execution States 365 Table amended m: Number of wait states in external device access Table 9.9 Number of States Required for Each Execution Status 10A.7.3 Pin Functions 412 to 414 Description replaced 10A.8.
Item Page Revision (See Manual for Details) 11.1.1 Features 543 Description amended • 18.3.5 Slave Receive Operation 878 Cascaded operation ⎯ Channel 1 (channel 4) input clock operates as 32-bit counter by setting channel 2 (channel 5) overflow/underflow Description added In slave receive mode, the master device outputs the transmit clock and transmit data, and the slave device returns an acknowledge signal.
Item Page 18.4 Usage Notes 893 Revision (See Manual for Details) Table amended 2 Table 18.8 I C Bus Timing (with Maximum Influence of tSr/tSf) Time Indication (at Maximum Transfer Rate) [ns] Item tcyc Indication tSDASO 1tSCLLO*3 −3tcyc (master) (−tSr ) Standard mode I2C Bus tSr/tSf SpecifiInfluence cation φ = (Max.) (Min.
Item Page Revision (See Manual for Details) 22.4.3 Flash Memory Operating Modes 945 Figure amended Notes: Only make a transition between user mode and user program mode when the CPU is not accessing the flash memory. Figure 22.3 Flash Memory State Transitions 22.7.2 ProgramVerify Mode 1. RAM emulation possible 2. This LSI transits to programmer mode by using the dedicated PROM programmer. 973 Figure amended Start of programming Programming must be executed in the erased state.
Item Page 22.7.4 Erase-Verify 975 Mode Revision (See Manual for Details) Figure amended Start Figure 22.
Item Page Revision (See Manual for Details) 22.11.3 Memory Read Mode ⎯ Description deleted 22.11.4 AutoProgram Mode ⎯ Description deleted 22.11.5 AutoErase Mode ⎯ Description deleted 22.11.6 Status Read Mode ⎯ Description deleted 22.11.7 Status Polling ⎯ Description deleted 22.11.8 Programmer Mode Transition Time ⎯ Description deleted 22.11.9 Notes on Memory Programming ⎯ Description deleted 23A.3.2 External Clock Input 1000 Table amended VCC = 3.0 V to 3.6 V, PVCC = 3.0 V to 5.
Item Page Revision (See Manual for Details) 24.1 Overview 1019 Figure amended Figure 24.1 (a) Mode Transition Diagram (H8S/2633 Group, H8S/2633R) Program execution state SSBY= 0, LSON= 0 SLEEP command High-speed mode (main clock) Sleep mode (main clock) Any interrupt SCK2 to SCK0= 0 SCK2 to SCK0 ≠ 0 Medium-speed mode (main clock) Figure 24.
Item Page Revision (See Manual for Details) 25.2 DC Characteristics 1049 Table amended Item Table 25.2 DC Characteristics (1) Current dissipation*2 1050 Typ Max Unit ICC*4 — 120 VCC = 3.0 V 200 μA Using 32.768 kHz crystal resonator Subsleep mode — 70 VCC = 3.0 V 150 μA Using 32.768 kHz crystal resonator Watch mode — 20 VCC = 3.0 V 50 μA Using 32.768 kHz crystal resonator Standby mode — 0.1 5.
Item Page Revision (See Manual for Details) 25.2 DC Characteristics 1053 Notes amended Notes: 2. When using P34 and P35 as output pins, set PVCC = 4.5 V to 5.5 V. Table 25.2 DC Characteristics (2) Table 25.3 1054 Permissible Output Currents Condition amended Conditions A: VCC = PLLVCC = 3.0 V to 3.6 V, PVCC = 3.0 V to 5.5 V, 1 2 AVCC = 3.6 V to 5.5 V* , Vref = 3.
Item Page Revision (See Manual for Details) 25.3.1 Clock Timing 1057 Condition amended Table 25.5 Clock Timing Condition A: VCC = PLLVCC = 3.0 V to 3.6 V, PVCC = 3.0 V to 5.5 V, 1 2 AVCC = 3.6 V to 5.5 V* , Vref = 3.6 V to AVCC* , VSS = AVSS = PLLVSS = 0 V, 2 to 16 MHz, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications) Condition B: VCC = PLLVCC = 3.0 V to 3.6 V, PVCC = 4.5 V to 5.5 V, AVCC = 4.5 V to 5.5 V, Vref = 4.
Item Page Revision (See Manual for Details) 25.4 A/D Conversion Characteristics 1083 Condition amended Condition A: VCC = PLLVCC = 3.0 V to 3.6 V, PVCC = 3.0 V to 5.5 V, 1 2 AVCC = 3.6 V to 5.5 V* , Vref = 3.6 V to AVCC* , VSS = AVSS = PLLVSS = 0 V, 2 to 16 MHz, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications) Condition B: VCC = PLLVCC = 3.0 V to 3.6 V, PVCC = 4.5 V to 5.5 V, AVCC = 4.5 V to 5.5 V, Vref = 4.
Item Page 25.6 Flash Memory 1086 Characteristics Table 25.13 Flash Memory Characteristics 26.2 DC Characteristics 1088 Revision (See Manual for Details) Notes amended Notes 4. Maximum programming time tP(max) = Wait time after P1 bit setting (z) × maximum number of writes (N) . = (z0 + z1) × N1 + z2 × N2 5. Maximum erase time tE(max) = Wait time after E1 bit setting (z) × maximum number of erases (N) = Z × N Table amended Symbol Min Typ Max VIH PVCC − 0.7 — PVCC + 0.
Item Page Revision (See Manual for Details) 26.2 DC Characteristics 1090 Notes amended Notes: 4. Table 26.2 DC Characteristics 26.3 AC Characteristics 1093 Figure amended C = 50 pF: Ports 10 to 13, 70 to 73, A to G (In case of expansion bus control signal output pin setting) C = 30 pF: All ports except ports 10 to 13, 70 to 73, A to G RL = 2.4 kΩ RH = 12 kΩ Input/output timing measurement levels • Low level: 0.8 V • High level: 2.0 V Figure 26.1 Output Load Circuit 26.3.
Item Page Revision (See Manual for Details) 26.6 Flash Memory 1121 Characteristics Table amended Item Symbol Min Typ Max Unit Table 26.
Item Page Revision (See Manual for Details) D.1 Port States in Each Mode 1422 Table amended Table D.1 I/O Port States in Each Processing State (H8S/2633, H8S/2632, H8S/2631, H8S/2633F, H8S/2633R) Table D.2 I/O Port 1426 States in Each Processing State (H8S/2695) R01UH0166EJ0600 Rev. 6.
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Contents Section 1 Overview .................................................................................................................. 1 1.1 1.2 1.3 Overview............................................................................................................................... 1 Internal Block Diagram......................................................................................................... 7 Pin Description ......................................................................
2.9 2.10 2.8.5 Bus-Released State ............................................................................................. 91 2.8.6 Power-Down State .............................................................................................. 91 Basic Timing....................................................................................................................... 92 2.9.1 Overview.............................................................................................................
4.4 4.5 4.6 4.7 Interrupts........................................................................................................................... 119 Trap Instruction................................................................................................................. 120 Stack Status after Exception Handling.............................................................................. 121 Notes on Use of the Stack..............................................................................
Section 6 PC Break Controller (PBC) (This function is not available in the H8S/2695) ..................................... 159 6.1 6.2 6.3 Overview .......................................................................................................................... 159 6.1.1 Features............................................................................................................. 159 6.1.2 Block Diagram.......................................................................................
7.4 7.5 7.6 7.7 7.8 7.9 7.10 7.3.2 Bus Specifications............................................................................................. 195 7.3.3 Memory Interfaces ............................................................................................ 196 7.3.4 Interface Specifications for Each Area ............................................................. 197 7.3.5 Chip Select Signals ...........................................................................................
7.11 7.12 Bus Arbitration (DMAC and DTC functions are not available in the H8S/2695) ........... 244 7.11.1 Overview........................................................................................................... 244 7.11.2 Operation .......................................................................................................... 244 7.11.3 Bus Transfer Timing......................................................................................... 245 Resets and the Bus Controller.....
8.5.10 8.5.11 8.5.12 8.5.13 8.5.14 8.6 8.7 DMAC Bus Cycles (Dual Address Mode)........................................................ 313 DMAC Bus Cycles (Single Address Mode) ..................................................... 321 Write Data Buffer Function .............................................................................. 327 DMAC Multi-Channel Operation .....................................................................
9.4 9.5 9.3.12 Examples of Use of the DTC ............................................................................ 367 Interrupts........................................................................................................................... 370 Usage Notes ...................................................................................................................... 370 Section 10A I/O Ports (H8S/2633, H8S/2632, H8S/2631, H8S/2633R) ................................ 371 10A.1 10A.
10A.10 10A.11 10A.12 10A.13 10A.9.3 Pin Functions for Each Mode ........................................................................ 434 10A.9.4 MOS Input Pull-Up Function ........................................................................ 436 Port D ............................................................................................................................. 437 10A.10.1 Overview ....................................................................................................
10B.7 10B.8 10B.9 10B.10 10B.11 10B.12 10B.13 10B.6.1 Overview ....................................................................................................... 492 10B.6.2 Register Configuration................................................................................... 493 10B.6.3 Pin Functions ................................................................................................. 493 Port A .....................................................................................
11.2 11.3 11.4 11.5 11.6 11.7 11.1.2 Block Diagram .................................................................................................. 547 11.1.3 Pin Configuration.............................................................................................. 548 11.1.4 Register Configuration...................................................................................... 550 Register Descriptions .......................................................................................
12.2 12.3 12.4 12.1.4 Registers ........................................................................................................... 640 Register Descriptions........................................................................................................ 641 12.2.1 Next Data Enable Registers H and L (NDERH, NDERL)................................ 641 12.2.2 Output Data Registers H and L (PODRH, PODRL)......................................... 642 12.2.
13.4.1 13.5 13.6 Interrupt Sources and DTC Activation (The H8S/2695 does not have a DTC function or an 8-bit timer)..................... 678 13.4.2 A/D Converter Activation................................................................................. 678 Sample Application........................................................................................................... 679 Usage Notes ..............................................................................................................
15.4 15.5 15.3.1 Watchdog Timer Operation .............................................................................. 717 15.3.2 Interval Timer Operation .................................................................................. 719 15.3.3 Timing of Setting Overflow Flag (OVF) .......................................................... 719 15.3.4 Timing of Setting of Watchdog Timer Overflow Flag (WOVF) ...................... 720 Interrupts..........................................................
Section 17 Smart Card Interface ...................................................................................... 803 17.1 17.2 17.3 17.4 Overview........................................................................................................................... 803 17.1.1 Features............................................................................................................. 803 17.1.2 Block Diagram ...............................................................................
2 18.4 18.3.1 I C Bus Data Format ......................................................................................... 866 18.3.2 Initial Setting .................................................................................................... 868 18.3.3 Master Transmit Operation ............................................................................... 868 18.3.4 Master Receive Operation................................................................................. 872 18.3.
20.3 20.2.1 D/A Data Registers 0 to 3 (DADR0 to DADR3) .............................................. 930 20.2.2 D/A Control Register 01 and 23 (DACR01 and DACR23) .............................. 930 20.2.3 Module Stop Control Register A and C (MSTPCRA and MSTPCRC) ............ 932 Operation .......................................................................................................................... 934 Section 21 RAM ............................................................................
22.7 22.8 22.9 22.10 22.11 22.12 22.13 22.14 22.6.1 Boot Mode ........................................................................................................ 962 22.6.2 User Program Mode.......................................................................................... 966 Programming/Erasing Flash Memory............................................................................... 968 22.7.1 Program Mode ...................................................................................
23B.2 23B.3 23B.4 23B.5 23B.6 23B.7 23B.8 23B.9 23B.1.1 Block Diagram............................................................................................. 1006 23B.1.2 Register Configuration................................................................................. 1006 Register Descriptions ................................................................................................... 1007 23B.2.1 System Clock Control Register (SCKCR) ...................................................
24.8 24.9 24.10 24.11 24.12 24.13 24.7.2 Hardware Standby Mode Timing.................................................................... 1039 Watch Mode (This function is not available in the H8S/2695)....................................... 1040 24.8.1 Watch Mode.................................................................................................... 1040 24.8.2 Exiting Watch Mode....................................................................................... 1041 24.8.3 Notes .......
26.4 26.5 26.6 26.7 A/D Conversion Characteristics...................................................................................... 1119 D/A Conversion Characteristics...................................................................................... 1120 Flash Memory Characteristics ........................................................................................ 1121 Usage Note..................................................................................................................
C.11 C.12 C.13 C.14 C.15 C.16 C.17 C.18 C.19 C.20 C.21 C.22 C.23 C.24 Port F Block Diagram ..................................................................................................... 1369 Port G Block Diagram .................................................................................................... 1377 Port 1 Block Diagram ..................................................................................................... 1381 Port 3 Block Diagram .....................................
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 1 Overview Section 1 Overview 1.1 Overview The H8S/2633 Group is a series of microcomputers (MCUs: microcomputer units), built around the H8S/2600 CPU, employing Renesas’ proprietary architecture, and equipped with peripheral functions on-chip.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 1 Overview Table 1.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Item Specification DMA controller 1 (DMAC)* • • • Data transfer 1 controller (DTC)* 16-bit timer-pulse unit (TPU) Programmable pulse generator 1 (PPG)* 8-bit timer* 4 channels 1 Watchdog timer 2 2 channels* 14-bit PWM timer 1 (PWM)* Serial communication interface (SCI) 5 channels (SCI0 to SCI4) • • • • • • • • Short address mode and full address mode selectable Short address mode: 4 channels Full address mode: 2 channels Transfe
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 1 Overview Item Specification IrDA-equipped SCI* • 1 channel (SCI0) • • • • 1 • • • Supports IrDA standard version 1.0 TxD and RxD encoding/decoding in IrDA format Start/stop synchronization mode or clock synchronization mode selectable Multiprocessor communications function Smart card interface function • • • Resolution: 10 bits Input: 16 channels High-speed conversion: 10.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 1 Overview Item Specification Power-down state • • • • • • Operating modes Four MCU operating modes Clock pulse generator Medium-speed mode Sleep mode Module stop mode Software standby mode Hardware standby mode 1 Subclock operation* (subactive mode, subsleep mode, watch mode) External Data Bus CPU Operating Description Mode Mode On-Chip ROM Initial Value Maximu m Value 4 On-chip ROM disabled expansion mode Disabled
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 1 Overview Item Specification Product lineup H8S/2633 Group, H8S/2633F, H8S/2633R, H8S/2695 Operating Frequencies and Voltages 28-MHz Operation Version 25-MHz Operation Version 16-MHz Operation Version Input clock frequency range 2 to 25 MHz 2 to 25 MHz 2 to 16 MHz Operating frequency range 2 to 25 MHz 2 to 25 MHz (For 25 to 28 MHzoperation, make sure to use a PLL with a multiplying factor set to ×2 or ×4.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 1 Overview Item Specification Product lineup Models and Corresponding Packages Model Name Package HD64F2633F25 FP-128B HD64F2633F16 HD6432633F25 HD6432633F16 HD6432632F25 HD6432632F16 HD6432631F25 HD6432631F16 HD64F2633RF28 HD6432695F28 HD64F2633TE25 TFP-120 HD64F2633TE16 HD6432633TE25 HD6432633TE16 HD6432632TE25 HD6432632TE16 HD6432631TE25 HD6432631TE16 HD64F2633RTE28 Notes: 1.
Port A PC7/ A7/PWM1 PC6/ A6/PWM0 PC5/ A5 PC4/ A4 PC3/ A3 PC2/ A2 PC1/ A1 PC0/ A0 8bit timer × 4 channels SCI × 5 channels (IrDA × 1channel) I2C bus interface (option) TPU Port B WDT × 2 channels RAM PB7/A15/TIOCB5 PB6/A14/TIOCA5 PB5/A13/TIOCB4 PB4/A12/TIOCA4 PB3 / A11/TIOCD3 PB2/A10/TIOCC3 PB1/A9/TIOCB3 PB0/A8/TIOCA3 14-bit PWM timer Port 3 Port F DMAC ROM (Mask ROM, flash memory*1) Peripheral address bus Bus controller PC break controller (2 channels) Peripheral data bus PE7 / D7 PE6 / D6 P
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Port A Port B PC7/A7/PWM1 PC6/A6/PWM0 PC5/A5 PC4/A4 PC3/A3 PC2/A2 PC1/A1 PC0/A0 8bit timer × 4 channels SCI × 5 channels (IrDA × 1channel) I2C bus interface (option) TPU Port C WDT × 2 channels RAM PB7/A15/TIOCB5 PB6/A14/TIOCA5 PB5/A13/TIOCB4 PB4/A12/TIOCA4 PB3 / A11/TIOCD3 PB2/A10/TIOCC3 PB1/A9/TIOCB3 PB0/A8/TIOCA3 14-bit PWM timer Port 3 Port F DMAC ROM (flash memory) Peripheral address bus Bus controller PC break controll
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 PE7/D7 PE6/D6 PE5/D5 PE4/D4 PE3/D3 PE2/D2 PE1/D1 PE0/D0 Port A Port B PB7 / A 1 5 /TIOCB5 PB6 / A 1 4 /TIOCA5 PB5 / A 1 3 /TIOCB4 PB4 / A 1 2 /TIOCA4 PB3 / A 1 1 /TIOCD3 PB2 / A 1 0 /TIOCC3 PB1 / A 9 /TIOCB3 PB0 / A 8 /TIOCA3 Port C PC7 / A 7 PC6 / A 6 PC5 / A 5 PC4 / A 4 PC3 / A 3 PC2 / A 2 PC1 / A 1 PC0 / A 0 Peripheral address bus Peripheral data bus Port F ROM (Mask ROM) PA3 /A19/SCK2 PA2 /A18/RxD2 PA1 /A17/TxD2 PA0 / A16 WDT ×
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 1.3 Pin Description 1.3.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 TOP VIEW (TFP-120) 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 P36/RxD4 P35/SCK1/SCK4/SCL0/IRQ5 P34/RxD1/SDA0 P33/TxD1/SCL1 VSS P32/SCK0/SDA1/IRQ4 PVCC2 P31/RxD0/IrRxD P30/TxD0/IrTxD PD7/D15 PD6/D14 PD5/
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 TOP VIEW (FP-128B) 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 P34/RxD1/SDA0 P33/TxD1/SCL1 VSS P32/SCK0/SDA1/IRQ4 PVCC2 P31/RxD0/IrRxD P30/TxD0/IrTxD PD7/D15 PD6/D14 PD5/D13 PD4/D12 PD3/D11 PD2/D
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 TOP VIEW (FP-128B) 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 P34/RxD1/SDA0 P33/TxD1/SCL1 VSS P32/SCK0/SDA1/IRQ4 PVCC2 P31/RxD0/IrRxD P30/TxD0/IrTxD PD7/D15 PD6/D14 PD5/D13 PD4/D12 PD3/D11 PD2/D10
MD1 MD2 NC NC PC0/A0 PC1/A1 PC2/A2 PC3/A3 VSS PC4/A4 VCL PC5/A5 PC6/A6 PC7/A7 VSS PB0/A8/TIOCA3 PVCC PB1/A9/TIOCB3 PB2/A10/TIOCC3 PB3/A11/TIOCD3 PB4/A12/TIOCA4 PB5/A13/TIOCB4 PB6/A14/TIOCA5 PB7/A15/TIOCB5 PA0/A16 PA1/A17/TxD2 PA2/A18/RxD2 PA3/A19/SCK2 VSS P10/TIOCA0/A20 P11/TIOCB0/A21 P12/TIOCC0/TCLKA/A22 P13/TIOCD0/TCLKB/A23 P14/TIOCA1/IRQ0 NC NC P15/TIOCB1/TCLKC P16/TIOCA2/IRQ1 Mar 02, 2011 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 6
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 1 Overview 1.3.2 Pin Functions in Each Operating Mode Table 1.2 (a) shows the pin functions of the H8S/2633, H8S/2633F, H8S/2632, and H8S/2631 in each of the operating modes. Table 1.2 (b) shows the pin functions of the H8S/2633R in each of the operating modes. Table 1.2 (c) shows the pin functions of the H8S/2695 in each of the operating modes. Table 1.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 1 Overview Pin No.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 1 Overview Pin No.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 1 Overview Pin No.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 1 Overview Pin No.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 1 Overview Table 1.2 (b) Pin Functions in Each Operating Mode (H8S/2633R) Pin No.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 1 Overview Pin No.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 1 Overview Pin No.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 1 Overview Pin No.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 1 Overview Pin No.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 1 Overview Table 1.2 (c) Pin Functions in Each Operating Mode (H8S/2695) Pin No.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 1 Overview Pin No.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 1 Overview Pin No.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 1 Overview Pin No.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 1 Overview Pin No.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 1.3.3 Section 1 Overview Pin Functions Table 1.3 (a) outlines the pin functions of the H8S/2633, H8S/2633F, H8S/2632, and H8S/2631. Table 1.3 (b) outlines the pin functions of the H8S/2633R. Table 1.3 (c) outlines the pin functions of the H8S/2695. Table 1.3 (a) Pin Functions (H8S/2633, H8S/2633F, H8S/2632, H8S/2631) Type Symbol I/O Name and Function Power VCC Input Power supply: For connection to the power supply.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 1 Overview Type Symbol I/O Name and Function Clock φ Output System clock: Supplies the system clock to an external device. Operating mode control MD2 to MD0 Input Mode pins: These pins set the operating mode. The relation between the settings of pins MD2 to MD0 and the operating mode is shown below. These pins should not be changed while the H8S/2633 Group is operating.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 1 Overview Type Symbol I/O Name and Function Interrupts NMI Input Nonmaskable interrupt: Requests a nonmaskable interrupt. When this pin is not used, it should be fixed high. IRQ7 to IRQ0 Input Interrupt request 7 to 0: These pins request a maskable interrupt. Address bus A23 to A0 Output Address bus: These pins output an address. Data bus D15 to D0 I/O Data bus: These pins constitute a bidirectional data bus.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 1 Overview Type Symbol I/O Name and Function DMA controller (DMAC) DREQ1, DREQ0 Input DMA request 1,0: Requests DMAC activation. TEND1, TEND0 Output DMA transfer completed 1,0: Indicates DMAC data transfer end. DACK1, DACK0 Output DMA transfer acknowledge 1,0: DMAC single address transfer acknowledge pin. TCLKD to TCLKA Input Clock input D to A: These pins input an external clock.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Type I/O Name and Function 14-bit PWM timer PWM0 to (PWMX) PWM3 Output PWMX timer output: PWM D/A pulse output pins. WDTOVF Output Watchdog timer overflows: The counter overflows signal output pin in watchdog timer mode. BUZZ Output BUZZ output: Output pins for the pulse divided by the watchdog timer. TxD4, TxD3, TxD2, TxD1, TxD0 Output Transmit data (channel 0 to 4): Data output pins.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 1 Overview Type Symbol I/O Name and Function A/D converter, D/A converter Vref Input A/D converter and D/A converter reference voltage input pin. When the A/D converter and D/A converter are not used, this pin should be connected to the system power supply (+5 V). I/O ports Page 36 of 1434 P17 to P10 I/O Port 1: An 8-bit I/O port.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 1 Overview Table 1.3 (b) Pin Functions (H8S/2633R) Type Symbol I/O Name and Function Power VCL Output On-chip power supply stabilizer pin: The VCL pin need not be connected to the power supply. Connect this pin to VSS via a 0.1 μF capacitor (placed close to the pins). PVCC1, PVCC2 Input Port power supply pin. Connect all pins to the same power supply. VSS Input Ground: For connection to ground (0 V).
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 1 Overview Type Symbol I/O Name and Function Operating mode control MD2 to MD0 Input Mode pins: These pins set the operating mode. The relation between the settings of pins MD2 to MD0 and the operating mode is shown below. These pins should not be changed while the H8S/2633 Group is operating.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 1 Overview Type Symbol I/O Name and Function Data bus D15 to D0 I/O Data bus: These pins constitute a bidirectional data bus. Bus control CS7 to CS0 Output Chip select: Selection signal for areas 0 to 7. AS Output Address strobe: When this pin is low, it indicates that address output on the address bus is enabled. RD Output Read: When this pin is low, it indicates that the external address space can be read.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 1 Overview Type Symbol I/O Name and Function 16-bit timerpulse unit (TPU) TCLKD to TCLKA Input Clock input D to A: These pins input an external clock. TIOCA0, TIOCB0, TIOCC0, TIOCD0 I/O Input capture/ output compare match A0 to D0: The TGR0A to TGR0D input capture input or output compare output, or PWM output pins.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 1 Overview Type Symbol I/O Name and Function Serial communication interface (SCI)/ Smart Card interface TxD4, TxD3, TxD2, TxD1, TxD0 Output Transmit data (channel 0 to 4): Data output pins. IrDA-equipped SCI 1 channel (SCI0) 2 I C bus interface (IIC) (optional) A/D converter RxD4, RxD3, Input RxD2, RxD1, RxD0 Receive data (channel 0 to 4): Data input pins.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 1 Overview Type Symbol I/O Name and Function I/O ports P17 to P10 I/O Port 1: An 8-bit I/O port. Input or output can be designated for each bit by means of the port 1 data direction register (P1DDR). P37 to P30 I/O Port 3: An 8-bit I/O port. Input or output can be designated for each bit by means of the port 3 data direction register (P3DDR). P47 to P40 Input Port 4: An 8-bit input port.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 1 Overview Table 1.3 (c) Pin Functions (H8S/2695) Type Symbol I/O Name and Function Power VCL Output On-chip power supply stabilizer pin: The VCL pin need not be connected to the power supply. Connect this pin to VSS via a 0.1 μF capacitor (placed close to the pins). PVCC Input Port power supply pin. Connect all pins to the same power supply. VSS Input Ground: For connection to ground (0 V).
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 1 Overview Type Symbol I/O Name and Function System control RES Input Reset input: When this pin is driven low, the chip is reset. MRES Input Manual reset: When this pin is driven low, a transmission is made to manual reset mode. STBY Input Standby: When this pin is driven low, a transition is made to hardware standby mode.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 1 Overview Type Symbol I/O Name and Function Bus control LWR Output Low write/lower column address strobe/lower write enable: A strobe signal that writes to external space and indicates that the lower half (D7 to D0) of the data bus is enabled. The 2CAS type (LCASS = 1) DRAM lower column address strobe signal. The 2WE type DRAM lower write enable signal.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 1 Overview Type Symbol I/O Name and Function Serial communication interface (SCI)/ Smart Card interface TxD4, TxD3, TxD2, TxD1, TxD0 Output Transmit data (channel 0, 1, 2): Data output pins. A/D converter RxD4, RxD3, Input RxD2, RxD1, RxD0 Receive data (channel 0, 1, 2): Data input pins. SCK4, SCK3, I/O SCK2, SCK1, SCK0 Serial clock (channel 0, 1, 2): Clock I/O pins. SCK0 output type is NMOS push-pull.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 1 Overview Type Symbol I/O Name and Function I/O ports PC7 to PC0 I/O Port C: An 8-bit I/O port. Input or output can be designated for each bit by means of the port C data direction register (PCDDR). PD7 to PD0 I/O Port D: An 8-bit I/O port. Input or output can be designated for each bit by means of the port D data direction register (PDDDR). PE7 to PE0 I/O Port E: An 8-bit I/O port.
Section 1 Overview Page 48 of 1434 H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 R01UH0166EJ0600 Rev. 6.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 2 CPU Section 2 CPU 2.1 Overview The H8S/2600 CPU is a high-speed central processing unit with an internal 32-bit architecture that is upward-compatible with the H8/300 and H8/300H CPUs. The H8S/2600 CPU has sixteen 16-bit general registers, can address a 16-Mbyte (architecturally 4-Gbyte) linear address space, and is ideal for realtime control. 2.1.1 Features The H8S/2600 CPU has the following features.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 2 CPU • High-speed operation ⎯ All frequently-used instructions execute in one or two states ⎯ Maximum clock rate: 25 MHz (H8S/2633, H8S/2633F, H8S/2632, H8S/2631), 28 MHz (H8S/2633R, H8S/2695) ⎯ 8/16/32-bit register-register add/subtract: 40 ns (25 MHz), 35 ns (28 MHz) ⎯ 8 • 8-bit register-register multiply: 120 ns (25 MHz), 105 ns (28 MHz) ⎯ 16 ÷ 8-bit register-register divide: 480 ns (25 MHz), 420 ns (28 MHz) ⎯ 16 • 16-bit
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 2 CPU Execution States Instruction Mnemonic H8S/2600 H8S/2000 MULXU MULXU.B Rs, Rd 3 12 MULXU.W Rs, ERd 4 20 MULXS.B Rs, Rd 4 13 MULXS.W Rs, ERd 5 21 MULXS In addition, there are differences in address space, CCR and EXR register functions, power-down modes, etc., depending on the model. 2.1.3 Differences from H8/300 CPU In comparison to the H8/300 CPU, the H8S/2600 CPU has the following enhancements.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 2 CPU 2.1.4 Differences from H8/300H CPU In comparison to the H8/300H CPU, the H8S/2600 CPU has the following enhancements.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 2 CPU (1) Normal Mode (Not Available in the H8S/2633 Group) The exception vector table and stack have the same structure as in the H8/300 CPU. Address Space: A maximum address space of 64 kbytes can be accessed. Extended Registers (En): The extended registers (E0 to E7) can be used as 16-bit registers, or as the upper 16-bit segments of 32-bit registers.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 2 CPU bit branch address. Branch addresses can be stored in the top area from H'0000 to H'00FF. Note that this area is also used for the exception vector table. Stack Structure: When the program counter (PC) is pushed onto the stack in a subroutine call, and the PC, condition-code register (CCR), and extended control register (EXR) are pushed onto the stack in exception handling, they are stored as shown in figure 2.3.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 2 CPU Exception Vector Table and Memory Indirect Branch Addresses: In advanced mode the top area starting at H'00000000 is allocated to the exception vector table in units of 32 bits. In each 32 bits, the upper 8 bits are ignored and a branch address is stored in the lower 24 bits (figure 2.4). For details of the exception vector table, see section 4, Exception Handling.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 2 CPU Stack Structure: In advanced mode, when the program counter (PC) is pushed onto the stack in a subroutine call, and the PC, condition-code register (CCR), and extended control register (EXR) are pushed onto the stack in exception handling, they are stored as shown in figure 2.5. When EXR is invalid, it is not pushed onto the stack. For details, see section 4, Exception Handling.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 2.3 Section 2 CPU Address Space Figure 2.6 shows a memory map of the H8S/2600 CPU. The H8S/2600 CPU provides linear access to a maximum 64-kbyte address space in normal mode, and a maximum 16-Mbyte (architecturally 4-Gbyte) address space in advanced mode.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 2 CPU 2.4 Register Configuration 2.4.1 Overview The CPU has the internal registers shown in figure 2.7. There are two types of registers: general registers and control registers.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 2.4.2 Section 2 CPU General Registers The CPU has eight 32-bit general registers. These general registers are all functionally alike and can be used as both address registers and data registers. When a general register is used as a data register, it can be accessed as a 32-bit, 16-bit, or 8-bit register. When the general registers are used as 32-bit registers or address registers, they are designated by the letters ER (ER0 to ER7).
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 2 CPU Free area SP (ER7) Stack area Figure 2.9 Stack 2.4.3 Control Registers The control registers are the 24-bit program counter (PC), 8-bit extended control register (EXR), 8-bit condition-code register (CCR), and 64-bit multiply-accumulate register (MAC). (1) Program Counter (PC) This 24-bit counter indicates the address of the next instruction the CPU will execute.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 2 CPU (3) Condition-Code Register (CCR) This 8-bit register contains internal CPU status information, including an interrupt mask bit (I) and half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags. Bit 7—Interrupt Mask Bit (I): Masks interrupts other than NMI when set to 1. (NMI is accepted regardless of the I bit setting.) The I bit is set to 1 by hardware at the start of an exceptionhandling sequence.
Section 2 CPU H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Operations can be performed on the CCR bits by the LDC, STC, ANDC, ORC, and XORC instructions. The N, Z, V, and C flags are used as branching conditions for conditional branch (Bcc) instructions. (4) Multiply-Accumulate Register (MAC) This 64-bit register stores the results of multiply-and-accumulate operations. It consists of two 32bit registers denoted MACH and MACL.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 2.5 Section 2 CPU Data Formats The CPU can process 1-bit, 4-bit (BCD), 8-bit (byte), 16-bit (word), and 32-bit (longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit n (n = 0, 1, 2, …, 7) of byte operand data. The DAA and DAS decimal-adjust instructions treat byte data as two digits of 4-bit BCD data. 2.5.1 General Register Data Formats Figure 2.10 shows the data formats in general registers.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 2 CPU Data Type Register Number Word data Rn Word data En Data Format 15 0 MSB 15 0 MSB Longword data LSB ERn 31 MSB LSB 16 15 En 0 LSB Rn Legend: ERn: General register ER En: General register E Rn: General register R RnH: General register RH RnL: General register RL MSB: Most significant bit LSB: Least significant bit Figure 2.10 General Register Data Formats (cont) Page 64 of 1434 R01UH0166EJ0600 Rev. 6.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 2.5.2 Section 2 CPU Memory Data Formats Figure 2.11 shows the data formats in memory. The CPU can access word data and longword data in memory, but word or longword data must begin at an even address. If an attempt is made to access word or longword data at an odd address, no address error occurs but the least significant bit of the address is regarded as 0, so the access starts at the preceding address.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 2 CPU 2.6 Instruction Set 2.6.1 Overview The H8S/2600 CPU has 69 types of instructions. The instructions are classified by function in table 2.1. Table 2.
Mar 02, 2011 R01UH0166EJ0600 Rev. 6.
Page 68 of 1434 — Bit manipulation — — — — — — B — B — — RTS TRAPA RTE SLEEP LDC STC ANDC, ORC, XORC NOP Block data transfer — B B — — — @ERn — — — W W — — — — — — B — — — @(d:16,ERn) — — — W W — — — — — — — — — — @(d:32,ERn) — — — W W — — — — — — — — — — — — — W W — — — — — — — — — — @–ERn/@ERn+ Notes: 1. Not available in the H8S/2633 Group. 2. When using the TAS instruction, use register ER0, ER1, ER4, or ER5. 3.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 2.6.3 Section 2 CPU Table of Instructions Classified by Function Table 2.3 summarizes the instructions in each functional category. The notation used in table 2.3 is defined below.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 2 CPU Table 2.3 Instructions Classified by Function Type Instruction 1 Size* Data transfer MOV B/W/L (EAs) → Rd, Rs → (Ead) Moves data between two general registers or between a general register and memory, or moves immediate data to a general register. MOVFPE B Cannot be used in the H8S/2633 Group. Arithmetic operations Page 70 of 1434 Function MOVTPE B Cannot be used in the H8S/2633 Group.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 2 CPU Type Instruction 1 Size* Arithmetic operations DAA DAS B Rd decimal adjust → Rd Decimal-adjusts an addition or subtraction result in a general register by referring to the CCR to produce 4-bit BCD data. MULXU B/W Rd × Rs → Rd Performs unsigned multiplication on data in two general registers: either 8 bits × 8 bits → 16 bits or 16 bits × 16 bits → 32 bits.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 2 CPU Type Instruction 1 Size* Arithmetic operations MAC — (EAs) × (EAd) + MAC → MAC Performs signed multiplication on memory contents and adds the result to the multiply-accumulate register. The following operations can be performed: 16 bits × 16 bits + 32 bits → 32 bits, saturating 16 bits × 16 bits + 42 bits → 42 bits, non-saturating CLRMAC — 0 → MAC Clears the multiply-accumulate register to zero.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 2 CPU Type Instruction 1 Size* Bitmanipulation instructions BSET B 1 → ( of ) Sets a specified bit in a general register or memory operand to 1. The bit number is specified by 3-bit immediate data or the lower three bits of a general register. BCLR B 0 → ( of ) Clears a specified bit in a general register or memory operand to 0.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 2 CPU Type Instruction 1 Size* Bitmanipulation instructions BXOR B C ⊕ ( of ) → C Exclusive-ORs the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag. BIXOR B C ⊕ [¬ ( of )] → C Exclusive-ORs the carry flag with the inverse of a specified bit in a general register or memory operand and stores the result in the carry flag.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 2 CPU Type Instruction 1 Size* Function Branch instructions Bcc — Branches to a specified address if a specified condition is true. The branching conditions are listed below.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 2 CPU Type Instruction 1 Size* Function System control TRAPA instructions RTE — Starts trap-instruction exception handling. — Returns from an exception-handling routine. SLEEP — Causes a transition to a power-down state. LDC B/W (EAs) → CCR, (EAs) → EXR Moves the source operand contents or immediate data to CCR or EXR. Although CCR and EXR are 8-bit registers, word-size transfers are performed between them and memory.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 2 CPU Type Instruction 1 Size* Block data transfer instruction EEPMOV.B — if R4L ≠ 0 then Repeat @ER5+ → @ER6+ R4L–1 → R4L Until R4L = 0 else next; EEPMOV.W — if R4 ≠ 0 then Repeat @ER5+ → @ER6+ R4–1 → R4 Until R4 = 0 else next; Function Transfers a data block according to parameters set in general registers R4L or R4, ER5, and ER6.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 2 CPU (4) Condition Field: Specifies the branching condition of Bcc instructions. Figure 2.12 shows examples of instruction formats. (1) Operation field only op NOP, RTS, etc. (2) Operation field and register fields op rm rn ADD.B Rn, Rm, etc. (3) Operation field, register fields, and effective address extension op rn rm MOV.B @(d:16, Rn), Rm, etc.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 2 CPU 2.7 Addressing Modes and Effective Address Calculation 2.7.1 Addressing Mode The CPU supports the eight addressing modes listed in table 2.4. Each instruction uses a subset of these addressing modes. Arithmetic and logic instructions can use the register direct and immediate modes. Data transfer instructions can use all addressing modes except program-counter relative and memory indirect.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 2 CPU (4) Register Indirect with Post-Increment or Pre-Decrement—@ERn+ or @-ERn: • Register indirect with post-increment—@ERn+ The register field of the instruction code specifies an address register (ERn) which contains the address of a memory operand. After the operand is accessed, 1, 2, or 4 is added to the address register contents and the sum is stored in the address register.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 2 CPU (6) Immediate—#xx:8, #xx:16, or #xx:32: The instruction contains 8-bit (#xx:8), 16-bit (#xx:16), or 32-bit (#xx:32) immediate data as an operand. The ADDS, SUBS, INC, and DEC instructions contain immediate data implicitly. Some bit manipulation instructions contain 3-bit immediate data in the instruction code, specifying a bit number.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 2 CPU Specified by @aa:8 Branch address Specified by @aa:8 Reserved Branch address (a) Normal Mode* (b) Advanced Mode Note: * Not available in the H8S/2633 Group. Figure 2.
Mar 02, 2011 R01UH0166EJ0600 Rev. 6.
Page 84 of 1434 6 op op abs abs abs op IMM Immediate #xx:8/#xx:16/#xx:32 @aa:32 op @aa:24 @aa:16 op abs Absolute address 5 @aa:8 Addressing Mode and Instruction Format No. Effective Address Calculation 24 23 24 23 24 23 24 23 87 16 15 Sign extension H'FFFF Operand is immediate data. Don’t care 31 Don’t care 31 Don’t care 31 Don’t care 31 Effective Address (EA) 0 0 0 0 Section 2 CPU H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 R01UH0166EJ0600 Rev.
R01UH0166EJ0600 Rev. 6.00 Mar 02, 2011 abs op abs • Advanced mode op • Normal mode* Memory indirect @@aa:8 op @(d:8, PC)/@(d:16, PC) Program-counter relative disp Addressing Mode and Instruction Format Note: * Not available in the H8S/2633 Group. 8 7 No.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 2 CPU 2.8 Processing States 2.8.1 Overview The CPU has five main processing states: the reset state, exception handling state, program execution state, bus-released state, and power-down state. Figure 2.14 shows a diagram of the processing states. Figure 2.15 indicates the state transitions. Reset state The CPU and all on-chip supporting modules have been initialized and are stopped.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 2 CPU End of bus request Bus request Program execution state ha nd lin g SLEEP instruction with SSBY = 0 pt ion s bu t of est es d En requ requ s Bu Sleep mode SLEEP instruction with SSBY = 1 e pt r rru Inte st que En d o ha f e x nd ce lin pti g on Re qu es tf or ex ce Bus-released state Exception handling state External interrupt request Software standby mode RES= High MRES= High STBY= High, RES= Low Manua
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 2 CPU 2.8.3 Exception-Handling State The exception-handling state is a transient state that occurs when the CPU alters the normal processing flow due to a reset, trace, interrupt, or trap instruction. The CPU fetches a start address (vector) from the exception vector table and branches to that address.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 2 CPU (2) Reset Exception Handling After the RES pin has gone low and the reset state has been entered, when RES pin goes high again, reset exception handling starts. After the reset state has been entered by driving the MRES pin low while manual resets are enabled by the MRESE bit, reset exception handling starts when MRES pin is driven high again.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 2 CPU Normal mode*2 EXR Reserved*1 SP SP CCR CCR*1 CCR CCR*1 PC (16 bits) PC (16 bits) (a) Interrupt control mode 0 (b) Interrupt control mode 2 Advanced mode SP SP EXR Reserved*1 CCR CCR PC (24 bits) PC (24 bits) (c) Interrupt control mode 0 (d) Interrupt control mode 2 Notes: 1. Ignored when returning. 2. Not available in the H8S/2633 Group. Figure 2.16 Stack Structure after Exception Handling (Examples) 2.8.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 2.8.5 Section 2 CPU Bus-Released State This is a state in which the bus has been released in response to a bus request from a bus master other than the CPU. While the bus is released, the CPU halts operations. Bus masters other than the CPU are DMA controller (DMAC)* and data transfer controller (DTC)*. For further details, refer to section 7, Bus Controller. Note: * DMAC and DTC functions are not available in the H8S/2695. 2.8.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 2 CPU 2.9 Basic Timing 2.9.1 Overview The H8S/2600 CPU is driven by a system clock, denoted by the symbol φ. The period from one rising edge of φ to the next is referred to as a "state." The memory cycle or bus cycle consists of one, two, or three states. Different methods are used to access on-chip memory, on-chip supporting modules, and the external address space. 2.9.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 2 CPU Bus cycle T1 φ Address bus Unchanged AS High RD High HWR, LWR High Data bus High-impedance state Figure 2.18 Pin States during On-Chip Memory Access 2.9.3 On-Chip Supporting Module Access Timing The on-chip supporting modules are accessed in two states. The data bus is either 8 bits or 16 bits wide, depending on the particular internal I/O register being accessed. Figure 2.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 2 CPU Bus cycle T1 T2 φ Internal address bus Address Internal read signal Read access Read data Internal data bus Internal write signal Write access Internal data bus Write data Figure 2.19 On-Chip Supporting Module Access Cycle Bus cycle T1 T2 φ Address bus Unchanged AS High RD High HWR, LWR High Data bus High-impedance state Figure 2.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 2.9.4 Section 2 CPU External Address Space Access Timing The external address space is accessed with an 8-bit or 16-bit data bus width in a two-state or three-state bus cycle. In three-state access, wait states can be inserted. For further details, refer to section 7, Bus Controller. 2.10 Usage Note 2.10.1 TAS Instruction Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction.
Section 2 CPU H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Page 96 of 1434 R01UH0166EJ0600 Rev. 6.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 3 MCU Operating Modes Section 3 MCU Operating Modes 3.1 Overview 3.1.1 Operating Mode Selection The H8S/2633 Group has four operating modes (modes 4 to 7). These modes enable selection of the CPU operating mode, enabling/disabling of on-chip ROM, and the initial bus width setting, by setting the mode pins (MD2 to MD0). Table 3.1 lists the MCU operating modes. Table 3.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 3 MCU Operating Modes Note that the functions of each pin depend on the operating mode. The H8S/2633 Group can be used only in modes 4 to 7. This means that the mode pins must be set to select one of these modes. Do not change the inputs at the mode pins during operation. 3.1.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 3 MCU Operating Modes levels are latched into these bits when MDCR is read. These latches are cancelled by a power-on reset, but maintained by a manual reset. 3.2.
Section 3 MCU Operating Modes H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Bit 3—NMI Edge Select (NMIEG): Selects the valid edge of the NMI interrupt input. Bit 3 NMIEG Description 0 An interrupt is requested at the falling edge of NMI input 1 An interrupt is requested at the rising edge of NMI input (Initial value) Bit 2—Manual Reset Selection Bit (MRESE): Enables or disables manual reset input. It is possible to set the P74/TM02/MRES pin to the manual reset input (MRES).
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 3 MCU Operating Modes Bit 0—RAM Enable (RAME): Enables or disables the on-chip RAM. The RAME bit is initialized when the reset status is released. It is not initialized in software standby mode. Bit 0 RAME Description 0 On-chip RAM is disabled 1 On-chip RAM is enabled Notes: When the DTC* is used, the RAME bit must be set to 1. * The DTC function is not available in the H8S/2695. 3.2.
Section 3 MCU Operating Modes H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Bit 6—CS3/CS6 Select (CSS36): Selects the CS output content for PG1 pin. In modes 4 to 6, the selected CS is output by setting the corresponding DDR to 1. Bit 6 CSS36 Description 0 Select CS3 1 Select CS6 (Initial value) Bit 5—BUZZ Output Enable (BUZZE)*: Disables/enables BUZZ output of PF1 pin. Input clock of WDT1 selected by PSS, CKS2 to CKS0 bits is output as a BUZZ signal.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 3 MCU Operating Modes Bit 3 Bit 2 Bit 1 Bit 0 AE3 AE2 AE1 AE0 Description 0 0 0 0 A8–A23 address output disabled 1 A8 address output enabled; A9–A23 address output disabled 0 A8, A9 address output enabled; A10–A23 address output disabled 1 A8–A10 address output enabled; A11–A23 address output disabled 0 A8–A11 address output enabled; A12–A23 address output disabled 1 A8–A12 address output enabled; A13–A23 a
Section 3 MCU Operating Modes 3.3 Operating Mode Descriptions 3.3.1 Mode 4 H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is disabled. Ports 1, A, B, and C, function as an address bus, ports D and E function as a data bus, and part of port F carries bus control signals. The initial bus mode after a reset is 16 bits, with 16-bit access to all areas.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 3.3.4 Section 3 MCU Operating Modes Mode 7 The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is enabled, but external addresses cannot be accessed. All I/O ports are available for use as input-output ports. 3.4 Pin Functions in Each Operating Mode The pin functions of ports A to G vary depending on the operating mode. Table 3.4 shows their functions in each operating mode. Table 3.
Section 3 MCU Operating Modes 3.5 H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Address Map in Each Operating Mode An address map of the H8S/2633, H8S/2633R are shown in figure 3.1, and an address map of the H8S/2632 in figure 3.2, and an address map of the H8S/2631 in figure 3.3, and an address map of the H8S/2695 in figure 3.4. The address space is 16 Mbytes in modes 4 to 7 (advanced modes). The address space is divided into eight areas for modes 4 to 7.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 3 MCU Operating Modes Modes 4 and 5 (advanced expanded modes with on-chip ROM disabled) Mode 6 (advanced expanded mode with on-chip ROM enabled) H'000000 H'000000 Mode 7 (advanced single-chip mode) H'000000 On-chip ROM External address space On-chip ROM H'03FFFF H'040000 External address space H'FFB000 H'FFB000 H'FFB000 On-chip RAM*1 On-chip RAM*1 On-chip RAM H'FFEFBF H'FFEFC0 External address space H'FFEFC0 H'F
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 3 MCU Operating Modes Modes 4 and 5 (advanced expanded modes with on-chip ROM disabled) H'000000 Mode 6 (advanced expanded mode with on-chip ROM enabled) Mode 7 (advanced single-chip mode) H'000000 H'000000 On-chip ROM On-chip ROM External address space H'02FFFF H'030000 Reserved area H'FFB000 H'FFC000 Reserved area H'040000 External address space H'FFB000 H'FFC000 Reserved area On-chip RAM*1 H'FFC000 On-chip RAM
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Modes 4 and 5 (advanced expanded modes with on-chip ROM disabled) H'000000 Section 3 MCU Operating Modes Mode 6 (advanced expanded mode with on-chip ROM enabled) Mode 7 (advanced single-chip mode) H'000000 H'000000 On-chip ROM On-chip ROM H'01FFFF H'020000 External address space Reserved area H'FFB000 H'FFD000 Reserved area H'040000 External address space H'FFB000 H'FFD000 Reserved area On-chip RAM*1 H'FFD000 On-chip RA
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 3 MCU Operating Modes Modes 4 and 5 (advanced expanded modes with on-chip ROM disabled) Mode 6 (advanced expanded mode with on-chip ROM enabled) H'000000 H'000000 H'000000 Mode 7 (advanced single-chip mode) On-chip ROM On-chip ROM External address space H'02FFFF H'030000 Reserved area H'FFB000 H'FFD000 Reserved area H'040000 External address space H'FFB000 H'FFD000 Reserved area On-chip RAM*1 H'FFD000 On-chip RAM
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 4 Exception Handling Section 4 Exception Handling 4.1 Overview 4.1.1 Exception Handling Types and Priority As table 4.1 indicates, exception handling may be caused by a reset, trace, direct transition, trap instruction, or interrupt. Exception handling is prioritized as shown in table 4.1. If two or more exceptions occur simultaneously, they are accepted and processed in order of priority.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 4 Exception Handling 4.1.2 Exception Handling Operation Exceptions originate from various sources. Trap instructions and interrupts are handled as follows: 1. The program counter (PC), condition code register (CCR), and extended register (EXR) are pushed onto the stack. 2. The interrupt mask bits are updated. The T bit is cleared to 0. 3.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Table 4.
Section 4 Exception Handling 4.2 Reset 4.2.1 Overview H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 A reset has the highest exception handling priority. There are two kinds of reset: a power-on reset executed via the RES pin, and a manual reset executed via the MRES pin. When the RES or MRES pin* goes low, currently executing processing is halted and the chip enters the reset state. A reset initializes the internal state of the CPU and the registers of on-chip supporting modules.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Table 4.3 Section 4 Exception Handling Types of Reset Conditions for Transition to Reset Internal State Type MRES RES CPU Built-in vicinity module Power-on reset * Low Initialization Initialization Manual reset Low High Initialization Initialization except for bus controller and I/O port *: Don't Care 4.2.3 Reset Sequence This LSI enters reset state when the RES pin or MRES pin goes low.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 4 Exception Handling Vector fetch * Internal processing Prefetch of first program instruction * * φ RES, MRES Address bus (1) (3) (5) RD High HWR, LWR D15 to D0 (2) (4) (6) (1) (3) Reset exception handling vector address (when power-on reset, (1) = H'000000*, (3) = H'000002; when manual reset, (1)= H'000004, (3)= H'000006) (2) (4) Start address (contents of reset exception handling vector address) (5) Start addres
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 4 Exception Handling Prefetch of Internal first program processing instruction Vector fetch φ RES, MRES (3) (1) Internal address bus (5) Internal read signal High Internal write signal Internal data bus (2) (4) (6) (1) (3) Reset exception handling vector address (when power-on reset, (1) = H'000000, (3) = H'000002) (2) (4) Start address (contents of reset exception handling vector address) (5) Start address ((5) = (2
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 4 Exception Handling 4.2.5 State of On-Chip Supporting Modules after Reset Release After reset release, MSTPCRA to MSTPCRC are initialized to H'3F, H'FF, and H'FF, respectively, and all modules except the DMAC* and DTC*, enter module stop mode. Consequently, on-chip supporting module registers cannot be read or written to. Register reading and writing is enabled when module stop mode is exited.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 4.4 Section 4 Exception Handling Interrupts Interrupt exception handling can be requested by nine external sources (NMI, IRQ7 to IRQ0) and 72 internal sources in the on-chip supporting modules. Figure 4.4 classifies the interrupt sources and the number of interrupts of each type.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 4 Exception Handling 4.5 Trap Instruction Trap instruction exception handling starts when a TRAPA instruction is executed. Trap instruction exception handling can be executed at all times in the program execution state. The TRAPA instruction fetches a start address from a vector table entry corresponding to a vector number from 0 to 3, as specified in the instruction code. Table 4.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 4.6 Section 4 Exception Handling Stack Status after Exception Handling Figure 4.5 shows the stack after completion of trap instruction exception handling and interrupt exception handling. SP SP CCR CCR* PC (16 bits) (a) Interrupt control mode 0 EXR Reserved* CCR CCR* PC (16 bits) (b) Interrupt control mode 2 Note: * Ignored on return. Figure 4.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 4 Exception Handling 4.7 Notes on Use of the Stack When accessing word data or longword data, the H8S/2633 Group assumes that the lowest address bit is 0. The stack should always be accessed by word transfer instruction or longword transfer instruction, and the value of the stack pointer (SP, ER7) should always be kept even. Use the following instructions to save registers: PUSH.W Rn (or MOV.W Rn, @-SP) PUSH.L ERn (or MOV.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 5 Interrupt Controller Section 5 Interrupt Controller 5.1 Overview 5.1.1 Features The H8S/2633 Group controls interrupts by means of an interrupt controller.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 5 Interrupt Controller 5.1.2 Block Diagram A block diagram of the interrupt controller is shown in Figure 5.1.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 5.1.3 Section 5 Interrupt Controller Pin Configuration Table 5.1 summarizes the pins of the interrupt controller. Table 5.1 Interrupt Controller Pins Name Symbol I/O Function Nonmaskable interrupt NMI Input Nonmaskable external interrupt; rising or falling edge can be selected External interrupt requests 7 to 0 IRQ7 to IRQ0 Input 5.1.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 5 Interrupt Controller 5.2 Register Descriptions 5.2.1 System Control Register (SYSCR) Bit : Initial value : R/W : 7 6 5 4 3 2 1 0 MACS — INTM1 INTM0 NMIEG MRESE — RAME 0 0 0 0 0 0 0 1 R/W — R/W R/W R/W R/W — R/W SYSCR is an 8-bit readable/writable register that selects the interrupt control mode, and the detected edge for NMI.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 5.2.2 Section 5 Interrupt Controller Interrupt Priority Registers A to L, O (IPRA to IPRL, IPRO) Bit : 7 6 5 4 3 2 1 0 — IPR6 IPR5 IPR4 — IPR2 IPR1 IPR0 Initial value : 0 1 1 1 0 1 1 1 R/W — R/W R/W R/W — R/W R/W R/W : The IPR registers are thirteen 8-bit readable/writable registers that set priorities (levels 7 to 0) for interrupts other than NMI.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 5 Interrupt Controller As shown in table 5.3, multiple interrupts are assigned to one IPR. Setting a value in the range from H'0 to H'7 in the 3-bit groups of bits 6 to 4 and 2 to 0 sets the priority of the corresponding interrupt. The lowest priority level, level 0, is assigned by setting H'0, and the highest priority level, level 7, by setting H'7.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 5.2.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 5 Interrupt Controller 5.2.5 IRQ Status Register (ISR) Bit : Initial value : R/W : 7 6 5 4 3 2 1 0 IRQ7F IRQ6F IRQ5F IRQ4F IRQ3F IRQ2F IRQ1F IRQ0F 0 0 0 0 0 0 0 0 R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* Note: * Only 0 can be written, to clear the flag. ISR is an 8-bit readable/writable register that indicates the status of IRQ7 to IRQ0 interrupt requests.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 5.3 Section 5 Interrupt Controller Interrupt Sources Interrupt sources comprise external interrupts (NMI and IRQ7 to IRQ0) and internal interrupts (72 sources). 5.3.1 External Interrupts There are nine external interrupts: NMI and IRQ7 to IRQ0. Of these, NMI and IRQ7 to IRQ0 can be used to restore the H8S/2633 Group from software standby mode.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 5 Interrupt Controller Figure 5.3 shows the timing of setting IRQnF. φ IRQn input pin IRQnF Figure 5.3 Timing of Setting IRQnF The vector numbers for IRQ7 to IRQ0 interrupt exception handling are 23 to 16. Detection of IRQ7 to IRQ0 interrupts does not depend on whether the relevant pin has been set for input or output.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 5 Interrupt Controller Table 5.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 5 Interrupt Controller Interrupt Source Origin of Interrupt Source TGI1A (TGR1A input capture/compare match) TPU channel 1 Vector Address* Vector Number Advanced Mode IPR Priority 40 H'00A0 IPRF2 to 0 High TGI1B (TGR1B input capture/compare match) 41 H'00A4 TCI1V (overflow 1) 42 H'00A8 TCI1U (underflow 1) 43 H'00AC 44 H'00B0 TGI2B (TGR2B input capture/compare match) 45 H'00B4 TCI2V (overflow 2) 46 H'00B8
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 5 Interrupt Controller Interrupt Source Origin of Interrupt Source TGI5A (TGR5A input capture/compare match) TPU channel 5 Vector Address* Vector Number Advanced Mode IPR Priority 60 H'00F0 IPRH2 to 0 High TGI5B (TGR5B input capture/compare match) 61 H'00F4 TCI5V (overflow 5) 62 H'00F8 TCI5U (underflow 5) 63 H'00FC 64 H'0100 65 H'0104 66 H'0108 CMIA0 (compare match A0) CMIB0 (compare match B0) 8-bit ti
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 5 Interrupt Controller Origin of Interrupt Source Vector Address* Vector Number Advanced Mode IPR Priority 88 H'0160 IPRK2 to 0 High 89 H'0164 TXI2 (transmit data empty 2) 90 H'0168 TEI2 (transmission end 2) 91 H'016C 92 H'0170 93 H'0174 94 H'0178 Interrupt Source ERI2 (receive error 2) RXI2 (reception completed 2) CMIA0 (compare match A2) CMIB0 (compare match B2) SCI channel 2 8 bit timer channel 2 OVI0 (
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 5 Interrupt Controller Origin of Interrupt Source Vector Address* Vector Number Advanced Mode IPR Priority 120 H'01E0 IPRO6 to 4 High 121 H'01E4 TXI3 (transmission data empty 3) 122 H'01E8 TEI3 (transmission end 3) 123 H'01EC 124 H'01F0 Interrupt Source ERI3 (reception error 3) RXI3 (reception completed 3) ERI4 (reception error 4) RXI4 (reception completed 4) SCI channel 3 SCI channel 4 125 H'01F4 TXI4 (t
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 5 Interrupt Controller Table 5.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 5 Interrupt Controller Interrupt Source Origin of Interrupt Source TGI1A (TGR1A input capture/compare match) TPU channel 1 Vector Address* Vector Number Advanced Mode IPR Priority 40 H'00A0 IPRF2 to 0 High TGI1B (TGR1B input capture/compare match) 41 H'00A4 TCI1V (overflow 1) 42 H'00A8 TCI1U (underflow 1) 43 H'00AC 44 H'00B0 TGI2B (TGR2B input capture/compare match) 45 H'00B4 TCI2V (overflow 2) 46 H'00
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 5 Interrupt Controller Interrupt Source Origin of Interrupt Source TGI5A (TGR5A input capture/compare match) TPU channel 5 Vector Address* Vector Number Advanced Mode IPR Priority 60 H'00F0 IPRH2 to 0 High TGI5B (TGR5B input capture/compare match) 61 H'00F4 TCI5V (overflow 5) 62 H'00F8 TCI5U (underflow 5) 63 H'00FC Reserved — 64 65 66 67 H'0100 H'0104 H'0108 H'010C IPRI6 to 4 Reserved — 68 69 70 71 H'011
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 5 Interrupt Controller Interrupt Source Origin of Interrupt Source Reserved Vector Address* Vector Number Advanced Mode — 92 93 94 95 96 97 98 99 Reserved — Reserved IPR Priority H'0170 H'0174 H'0178 H'017C H'0180 H'0184 H'0188 H'018C IPRL6 to 4 High 100 101 102 103 H'0190 H'0194 H'0198 H'019C IPRL2 to 0 — 104 105 106 107 H'01A0 H'01A4 H'01A8 H'01AC IPRM6 to 4 Reserved — 108 109 110 111 H'01B0 H'01B4 H'01
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 5 Interrupt Controller 5.4 Interrupt Operation 5.4.1 Interrupt Control Modes and Interrupt Operation Interrupt operations in the H8S/2633 Group differ depending on the interrupt control mode. NMI interrupts are accepted at all times except in the reset state and the hardware standby state. In the case of IRQ interrupts and on-chip supporting module interrupts, an enable bit is provided for each interrupt.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 5 Interrupt Controller Figure 5.4 shows a block diagram of the priority decision circuit. Interrupt control mode 0 I Interrupt acceptance control Default priority determination Interrupt source Vector number 8-level mask control IPR I2 to I0 Interrupt control mode 2 Figure 5.4 Block Diagram of Interrupt Control Operation R01UH0166EJ0600 Rev. 6.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 5 Interrupt Controller (1) Interrupt Acceptance Control In interrupt control mode 0, interrupt acceptance is controlled by the I bit in CCR. Table 5.6 shows the interrupts selected in each interrupt control mode. Table 5.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 5 Interrupt Controller (3) Default Priority Determination When an interrupt is selected by 8-level control, its priority is determined and a vector number is generated. If the same value is set for IPR, acceptance of multiple interrupts is enabled, and so only the interrupt source with the highest priority according to the preset default priorities is selected and has a vector number generated.
Section 5 Interrupt Controller 5.4.2 H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Interrupt Control Mode 0 Enabling and disabling of IRQ interrupts and on-chip supporting module interrupts can be set by means of the I bit in the CPU’s CCR. Interrupts are enabled when the I bit is cleared to 0, and disabled when set to 1. Figure 5.5 shows a flowchart of the interrupt acceptance operation in this case.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 5 Interrupt Controller Program execution status No Interrupt generated? Yes Yes NMI No No I=0 Hold pending Yes No IRQ0 Yes IRQ1 No Yes TEI4 Yes Save PC and CCR I←1 Read vector address Branch to interrupt handling routine Figure 5.5 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Mode 0 R01UH0166EJ0600 Rev. 6.
Section 5 Interrupt Controller 5.4.3 H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Interrupt Control Mode 2 Eight-level masking is implemented for IRQ interrupts and on-chip supporting module interrupts by comparing the interrupt mask level set by bits I2 to I0 of EXR in the CPU with IPR. Figure 5.6 shows a flowchart of the interrupt acceptance operation in this case.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 5 Interrupt Controller Program execution status Interrupt generated? No Yes Yes NMI No Level 7 interrupt? No Yes Mask level 6 or below? Yes Level 6 interrupt? No No Yes Mask level 5 or below? Level 1 interrupt? No No Yes Yes Mask level 0? No Yes Save PC, CCR, and EXR Hold pending Clear T bit to 0 Update mask level Read vector address Branch to interrupt handling routine Figure 5.
Page 150 of 1434 (1) (2) (4) (3) Internal operation Instruction prefetch address (Not executed. This is the contents of the saved PC, the return address.) (2) (4) Instruction code (Not executed.) (3) Instruction prefetch address (Not executed.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 5.4.5 Section 5 Interrupt Controller Interrupt Response Times The H8S/2633 Group is capable of fast word transfer instruction to on-chip memory, and the program area is provided in on-chip ROM and the stack area in on-chip RAM, enabling highspeed processing. Table 5.9 shows interrupt response times—the interval between generation of an interrupt request and execution of the first instruction in the interrupt handling routine.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 5 Interrupt Controller Table 5.10 Number of States in Interrupt Handling Routine Execution Statuses Object of Access External Device 8 Bit Bus Symbol Instruction fetch SI Branch address read SJ Stack manipulation SK 16 Bit Bus Internal Memory 2-State Access 3-State Access 2-State Access 3-State Access 1 4 6+2m 2 3+m Legend: m: Number of wait states in an external device access. 5.5 Usage Notes 5.5.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 5 Interrupt Controller TCR write cycle by CPU CMIA exception handling φ Internal address bus TCR address Internal write signal CMIEA CMFA CMIA interrupt signal Figure 5.8 Contention between Interrupt Generation and Disabling The above contention will not occur if an enable bit or interrupt source flag is cleared to 0 while the interrupt is masked. 5.5.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 5 Interrupt Controller 5.5.4 Interrupts during Execution of EEPMOV Instruction Interrupt operation differs between the EEPMOV.B instruction and the EEPMOV.W instruction. With the EEPMOV.B instruction, an interrupt request (including NMI) issued during the transfer is not accepted until the move is completed. With the EEPMOV.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 5 Interrupt Controller 5.6 DTC and DMAC Activation by Interrupt (DMAC and DTC functions are not available in the H8S/2695) 5.6.1 Overview The DTC and DMAC can be activated by an interrupt.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 5 Interrupt Controller 5.6.2 Block Diagram Figure 5.9 shows a block diagram of the DTC and DMAC interrupt controller.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 5.6.3 Section 5 Interrupt Controller Operation (DMAC and DTC functions are not available in the H8S/2695) The interrupt controller has three main functions in DTC and DMAC control. (1) Selection of Interrupt Source: DMAC inputs activation factor directly to each channel. The activation factors for each channel of DMAC are selected by DTF3 to DTF0 bits of DMACR.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 5 Interrupt Controller Table 5.11 Interrupt Source Selection and Clearing Control Settings 1 DMAC* 1 DTC* 1 DTA* 1 DTCE* 1 DISEL* 0 0 1 Interrupt Source Selection/Clearing Control 1 DMAC* 1 DTC* CPU * X Δ 0 Δ X Δ 1 1 * * Δ X X Legend: Δ: The relevant interrupt is used. Interrupt source clearing is performed. (The CPU should clear the source flag in the interrupt handling routine.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 6 PC Break Controller (PBC) (This function is not available in the H8S/2695) Section 6 PC Break Controller (PBC) (This function is not available in the H8S/2695) 6.1 Overview The PC break controller (PBC) provides functions that simplify program debugging. Using these functions, it is easy to create a self-monitoring debugger, enabling programs to be debugged with the chip alone, without using an in-circuit emulator.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 6 PC Break Controller (PBC) (This function is not available in the H8S/2695) 6.1.2 Block Diagram Figure 6.1 shows a block diagram of the PC break controller. BARA Mask control Output control BCRA Control logic Comparator Match signal Internal address Control logic Comparator Match signal Mask control BARB Output control Access status PC break interrupt BCRB Figure 6.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 6.1.3 Section 6 PC Break Controller (PBC) (This function is not available in the H8S/2695) Register Configuration Table 6.1 shows the PC break controller registers. Table 6.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 6 PC Break Controller (PBC) (This function is not available in the H8S/2695) 6.2.3 Break Control Register A (BCRA) Bit : Initial value : 7 6 CMFA CDA 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W : R/(W)* R/W 5 4 3 2 1 0 BAMRA2 BAMRA1 BAMRA0 CSELA1 CSELA0 BIEA Note: * Only 0 can be written, for flag clearing. BCRA is an 8-bit readable/writable register that controls channel A PC breaks.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Bit 5 Bit 4 Section 6 PC Break Controller (PBC) (This function is not available in the H8S/2695) Bit 3 BAMRA2 BAMRA1 BAMRA0 Description 0 0 1 1 0 1 0 All BARA bits are unmasked and included in break conditions (Initial value) 1 BAA0 (lowest bit) is masked, and not included in break conditions 0 BAA1 to BAA0 (lower 2 bits) are masked, and not included in break conditions 1 BAA2 to BAA0 (lower 3 bits) are masked, and not in
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 6 PC Break Controller (PBC) (This function is not available in the H8S/2695) 6.2.4 Break Control Register B (BCRB) BCRB is the channel B break control register. The bit configuration is the same as for BCRA. 6.2.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 6.3 Section 6 PC Break Controller (PBC) (This function is not available in the H8S/2695) Operation The operation flow from break condition setting to PC break interrupt exception handling is shown in sections 6.3.1, PC Break Interrupt Due to Instruction Fetch, and 6.3.2, PC Break Interrupt Due to Data Access, taking the example of channel A. 6.3.
Section 6 PC Break Controller (PBC) (This function is not available in the H8S/2695) 6.3.2 H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 PC Break Interrupt Due to Data Access (1) Initial settings ⎯ Set the break address in BARA. For a PC break caused by a data access, set the target ROM, RAM, I/O, or external address space address as the break address. Stack operations and branch address reads are included in data accesses. ⎯ Set the break conditions in BCRA.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 6.3.4 Section 6 PC Break Controller (PBC) (This function is not available in the H8S/2695) Operation in Transitions to Power-Down Modes The operation when a PC break interrupt is set for an instruction fetch at the address after a SLEEP instruction is shown below.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 6 PC Break Controller (PBC) (This function is not available in the H8S/2695) SLEEP instruction execution SLEEP instruction execution SLEEP instruction execution SLEEP instruction execution PC break exception handling System clock → subclock Subclock → system clock, oscillation settling time Transition to respective mode Execution of instruction after sleep instruction Direct transition exception handling Direct transition
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 6.3.6 Section 6 PC Break Controller (PBC) (This function is not available in the H8S/2695) When Instruction Execution Is Delayed by One State Caution is required in the following cases, as instruction execution is one state later than usual. (1) When the PBC is enabled (i.e.
Section 6 PC Break Controller (PBC) (This function is not available in the H8S/2695) 6.3.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 7 Bus Controller Section 7 Bus Controller 7.1 Overview The H8S/2633 Group has a built-in bus controller (BSC) that manages the external address space divided into eight areas. The bus specifications, such as bus width and number of access states, can be set independently for each area, enabling multiple memories to be connected easily.
Section 7 Bus Controller H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 • Idle cycle insertion ⎯ An idle cycle can be inserted in case of an external read cycle between different areas ⎯ An idle cycle can be inserted in case of an external write cycle immediately after an external read cycle • Write buffer functions ⎯ External write cycle and internal access can be executed in parallel ⎯ DMAC* single-address mode and internal access can be executed in parallel • Bus arbitration functi
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 7.1.2 Section 7 Bus Controller Block Diagram Figure 7.1 shows a block diagram of the bus controller.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 7 Bus Controller 7.1.3 Pin Configuration Table 7.1 summarizes the pins of the bus controller. Table 7.1 Bus Controller Pins Name Symbol I/O Function Address strobe AS Output Strobe signal indicating that address output on address bus is enabled. Read RD Output Strobe signal indicating that external space is being read.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 7 Bus Controller Name Symbol I/O Function Lower column strobe* LCAS* Output DRAM lower column address strobe signal* Wait WAIT Input Wait request signal when accessing external 3-state access space. Bus request BREQ Input Request signal that releases bus to external device. Bus request acknowledge BACK Output Acknowledge signal indicating that bus has been released.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 7 Bus Controller 7.2 Register Descriptions 7.2.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 7.2.2 Section 7 Bus Controller Access State Control Register (ASTCR) Bit : Initial value : R/W : 7 6 5 4 3 2 1 0 AST7 AST6 AST5 AST4 AST3 AST2 AST1 AST0 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W ASTCR is an 8-bit readable/writable register that designates each area as either a 2-state access space or a 3-state access space. ASTCR sets the number of access states for the external memory space.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 7 Bus Controller 7.2.3 Wait Control Registers H and L (WCRH, WCRL) WCRH and WCRL are 8-bit readable/writable registers that select the number of program wait states for each area. Program waits are not inserted in the case of on-chip memory or internal I/O registers. WCRH and WCRL are initialized to H'FF by a power-on reset and in hardware standby mode. They are not initialized by a manual reset or in software standby mode.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 7 Bus Controller Bits 5 and 4—Area 6 Wait Control 1 and 0 (W61, W60): These bits select the number of program wait states when area 6 in external space is accessed while the AST6 bit in ASTCR is set to 1.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 7 Bus Controller (2) WCRL Bit : Initial value : R/W : 7 6 5 4 3 2 1 0 W31 W30 W21 W20 W11 W10 W01 W00 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W Bits 7 and 6—Area 3 Wait Control 1 and 0 (W31, W30): These bits select the number of program wait states when area 3 in external space is accessed while the AST3 bit in ASTCR is set to 1.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 7 Bus Controller Bit 3 Bit 2 W11 W10 Description 0 0 Program wait not inserted when external space area 1 is accessed 1 1 program wait state inserted when external space area 1 is accessed 0 2 program wait states inserted when external space area 1 is accessed 1 3 program wait states inserted when external space area 1 is accessed (Initial value) 1 Bits 1 and 0—Area 0 Wait Control 1 and 0 (W01, W00): These bits sel
Section 7 Bus Controller H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Bit 7—Idle Cycle Insert 1 (ICIS1): Selects whether or not one idle cycle state is to be inserted between bus cycles when successive external read cycles are performed in different areas.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 7 Bus Controller Bit 3—Burst Cycle Select 0 (BRSTS0): Selects the number of words that can be accessed in a burst ROM interface burst access. Bit 3 BRSTS0 Description 0 Max. 4 words in burst access 1 Max. 8 words in burst access (Initial value) Bits 2 to 0—RAM Type Select (RMTS2 to RMTS0): In advanced mode, these bits select the memory interface for areas 2 to 5.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 7 Bus Controller 7.2.5 Bit Bus Control Register L (BCRL) : Initial value : R/W : 7 6 5 4 3 2 1 0 BRLE BREQOE — OES* DDS* RCTS* WDBE WAITE 0 0 0 0 1 0 0 0 R/W R/W — R/W R/W R/W R/W R/W Note: * This function is not available in the H8S/2695. In writing to OES, DDS, RCTS, the initial value should be written to these bits.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 7 Bus Controller Bit 4—OE Select (OES): Selects the CS3 pin as the OE pin. Bit 4 OES Description 0 Uses the CS3 pin as the port or as CS3 signal output 1 When only area 2 is set for DRAM, or when areas 2 to 5 are set as contiguous DRAM space, the CS3 pin is used as the OE pin (Initial value) Bit 3—DACK Timing Select (DDS): When using the DRAM interface, this bit selects the DMAC single address transfer bus timing.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 7 Bus Controller Bit 0—WAIT Pin Enable (WAITE): Selects enabling or disabling of wait input by the WAIT pin. Bit 0 WAITE Description 0 Wait input by WAIT pin disabled. WAIT pin can be used as I/O port 1 Wait input by WAIT pin enabled 7.2.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 7 Bus Controller Bit 6—CS3/CS6 Select (CSS36): This bit selects the contents of CS output via the PG1 pin. In modes 4, 5, and 6, setting the corresponding DDR to 1 outputs the selected CS. Bit 6 CSS36 Description 0 Selects CS3 1 Selects CS6 (Initial value) Bit 5—BUZZ Output Enable (BUZZE): This bit enables/disables BUZZ output via the PF1 pin.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 7 Bus Controller Bit 3 Bit 2 Bit 1 Bit 0 AE3 AE2 AE1 AE0 Description 0 0 0 0 A8 to A23 address output disabled 1 A8 address output enabled; A9 to A23 address output disabled 0 A8, A9 address output enabled; A10 to A23 address output disabled 1 A8 to A10 address output enabled; A11 to A23 address output disabled 0 A8 to A11 address output enabled; A12 to A23 address output disabled 1 A8 to A12 address output en
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 7.2.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 7 Bus Controller Bit 5 RCDM Description 0 DRAM interface: selects RAS up mode 1 DRAM interface: selects RAS down mode (Initial value) Bit 4—Reserved (CW2): Only write 0 to this bit. Bits 3 and 2—Multiplex shift counts 1 and 0 (MXC1 and MXC0): These bits select the shift amount to the low side of the row address of the multiplexed row/column address in DRAM interface mode.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 7.2.8 Section 7 Bus Controller DRAM Control Register (DRAMCR)* Bit : Initial value : R/W : 7 6 5 4 3 2 1 0 RFSHE CBRM RMODE CMF CMIE CKS2 CKS1 CKS0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W The DRAMCR is an 8-bit read/write register that selects DRAM refresh mode, the refresh counter clock, and sets the refresh timer control.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 7 Bus Controller Bit 4—Compare Match Flag (CMF): This status flag shows a match between RTCNT and RTCOR values. When performing refresh control (RFSHE=1), write 1 to CMF when writing to the DRAMCR.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 7.2.9 Section 7 Bus Controller Refresh Timer Counter (RTCNT)* Bit : Initial value : R/W : 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W RTCNT is an 8-bit read/write up-counter. RTCNT counts up using the internal clock selected by the DRAMCR CKS2 to CKS0 bits. When RTCNT matches the value in RTCOR (compare match), the DRAMCR CMF flag is set to 1 and RTCNT is cleared to H'00.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 7 Bus Controller 7.3 Overview of Bus Control 7.3.1 Area Partitioning In advanced mode, the bus controller partitions the 16 Mbytes address space into eight areas, 0 to 7, in 2-Mbyte units, and performs bus control for external space in area units. A chip select signal (CS0 to CS7) can be output for each area. In normal mode*, it controls a 64-kbyte address space comprising part of area 0. Figure 7.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 7.3.2 Section 7 Bus Controller Bus Specifications The external space bus specifications consist of three elements: bus width, number of access states, and number of program wait states. The bus width and number of access states for on-chip memory and internal I/O registers are fixed, and are not affected by the bus controller. (1) Bus Width: A bus width of 8 or 16 bits can be selected with ABWCR.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 7 Bus Controller Table 7.3 Bus Specifications for Each Area (Basic Bus Interface) ABWCR ASTCR WCRH, WCRL Bus Specifications (Basic Bus Interface) ABWn ASTn Wn1 Wn0 Bus Width Program Wait Access States States 0 0 — — 16 2 0 1 0 0 3 0 1 1 1 0 2 1 3 0 — — 1 0 0 1 7.3.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 7.3.4 Section 7 Bus Controller Interface Specifications for Each Area The initial state of each area is basic bus interface, 3-state access space. The initial bus width is selected according to the operating mode. The bus specifications described here cover basic items only, and the sections on each memory interface (section 7.4, Basic Bus Interface, section 7.5, DRAM Interface, and section 7.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 7 Bus Controller 7.3.5 Chip Select Signals This LSI allows chip select signals (CS0 to CS7) to be output for each of areas 0 to 7. The level of these signals is set Low when accessing the external space of the respective area. Figure 7.3 shows example CSn (where n = 0 to 7) signal output timing. The output of the CSn signal can be enabled or disabled by the data direction register (DDR) of the port of the corresponding CSn pin.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 7.4 Basic Bus Interface 7.4.1 Overview Section 7 Bus Controller The basic bus interface enables direct connection of ROM, SRAM, and so on. The bus specifications can be selected with ABWCR, ASTCR, WCRH, and WCRL (see table 7.3). 7.4.2 Data Size and Data Alignment Data sizes for the CPU and other internal bus masters are byte, word, and longword.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 7 Bus Controller 16-Bit Access Space: Figure 7.5 illustrates data alignment control for the 16-bit access space. With the 16-bit access space, the upper data bus (D15 to D8) and lower data bus (D7 to D0) are used for accesses. The amount of data that can be accessed at one time is one byte or one word, and a longword transfer instruction is executed as two word transfer instructions.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 7.4.3 Section 7 Bus Controller Valid Strobes Table 7.4 shows the data buses used and valid strobes for the access spaces. In a read, the RD signal is valid without discrimination between the upper and lower halves of the data bus. In a write, the HWR signal is valid for the upper half of the data bus, and the LWR signal for the lower half. Table 7.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 7 Bus Controller 7.4.4 Basic Timing 8-Bit 2-State Access Space: Figure 7.6 shows the bus timing for an 8-bit 2-state access space. When an 8-bit access space is accessed, the upper half (D15 to D8) of the data bus is used. The LWR pin is fixed high. Wait states cannot be inserted.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 7 Bus Controller 8-Bit 3-State Access Space: Figure 7.7 shows the bus timing for an 8-bit 3-state access space. When an 8-bit access space is accessed, the upper half (D15 to D8) of the data bus is used. The LWR pin is fixed high. Wait states can be inserted.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 7 Bus Controller 16-Bit 2-State Access Space: Figures 7.8 to 7.10 show bus timings for a 16-bit 2-state access space. When a 16-bit access space is accessed, the upper half (D15 to D8) of the data bus is used for the even address, and the lower half (D7 to D0) for the odd address. Wait states cannot be inserted.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 7 Bus Controller Bus cycle T1 T2 φ Address bus CSn AS RD Read D15 to D8 Invalid D7 to D0 Valid HWR High LWR Write D15 to D8 D7 to D0 High impedance Valid Note: n = 0 to 7 Figure 7.9 Bus Timing for 16-Bit 2-State Access Space (2) (Odd Address Byte Access) R01UH0166EJ0600 Rev. 6.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 7 Bus Controller Bus cycle T1 T2 φ Address bus CSn AS RD Read D15 to D8 Valid D7 to D0 Valid HWR LWR Write D15 to D8 Valid D7 to D0 Valid Note: n = 0 to 7 Figure 7.10 Bus Timing for 16-Bit 2-State Access Space (3) (Word Access) Page 206 of 1434 R01UH0166EJ0600 Rev. 6.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 7 Bus Controller 16-Bit 3-State Access Space: Figures 7.11 to 7.13 show bus timings for a 16-bit 3-state access space. When a 16-bit access space is accessed, the upper half (D15 to D8) of the data bus is used for the even address, and the lower half (D7 to D0) for the odd address. Wait states can be inserted.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 7 Bus Controller Bus cycle T1 T2 T3 φ Address bus CSn AS RD Read D15 to D8 Invalid D7 to D0 Valid HWR High LWR Write D15 to D8 D7 to D0 High impedance Valid Note: n = 0 to 7 Figure 7.12 Bus Timing for 16-Bit 3-State Access Space (2) (Odd Address Byte Access) Page 208 of 1434 R01UH0166EJ0600 Rev. 6.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 7 Bus Controller Bus cycle T1 T2 T3 φ Address bus CSn AS RD Read D15 to D8 Valid D7 to D0 Valid HWR LWR Write D15 to D8 Valid D7 to D0 Valid Note: n = 0 to 7 Figure 7.13 Bus Timing for 16-Bit 3-State Access Space (3) (Word Access) R01UH0166EJ0600 Rev. 6.
Section 7 Bus Controller 7.4.5 H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Wait Control When accessing external space, the H8S/2633 Group can extend the bus cycle by inserting one or more wait states (Tw). There are two ways of inserting wait states: program wait insertion and pin wait insertion using the WAIT pin.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 7 Bus Controller Figure 7.14 shows an example of wait state insertion timing. By program wait T1 T2 Tw By WAIT pin Tw Tw T3 φ WAIT Address bus AS RD Read Data bus Read data HWR, LWR Write Data bus Note: Write data indicates the timing of WAIT pin sampling. Figure 7.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 7 Bus Controller 7.5 DRAM Interface (This function is not available in the H8S/2695) 7.5.1 Overview This LSI allows area 2 to 5 external space to be set as DRAM space and DRAM interfacing to be performed. With the DRAM interface, DRAM can be directly connected to the LSI. BCRH RMTS2 to RMTS0 allow the setting up of 2, 4, or 8MB DRAM space. Burst operation is possible using high-speed page mode. 7.5.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 7.5.3 Section 7 Bus Controller Address Multiplexing In the case of DRAM space, the row address and column address are multiplexed. With address multiplexing, the MXC1 and MXC0 bits of the MCR select the amount of shift in the row address. Table 7.6 shows the relationship between MXC1 and MXC0 settings and the shift amount. Table 7.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 7 Bus Controller 7.5.5 DRAM Interface Pins Table 7.7 shows the pins used for the DRAM interface, and their functions. Table 7.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 7 Bus Controller The four basic timing states are as follows: TP (precharge cycle) 1 state, Tr (row address output cycle) 1 state, Tc1 and Tc2 (column address output cycle) two states. When RCTS is set to 1, the CAS signal timing differs when reading and writing, being asserted Ω cycle earlier when reading.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 7 Bus Controller 7.5.7 Precharge State Control When accessing DRAM, it is essential to secure a time for RAS precharging. In this LSI, it is therefore necessary to insert 1 TP state when accessing DRAM space. By setting the TPC bit of the MCR to 1, TP can be changed from 1 state to 2 states. Set the appropriate number of TP cycles according to the type of DRAM connected and the operation frequency of the LSI. Figure 7.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 7.5.8 Section 7 Bus Controller Wait Control There are two methods of inserting wait states in DRAM access: (1) insertion of program wait states, and (2) insertion of pin waits via WAIT pin. (1) Insertion of Program Wait States Setting the ASTCR bit of an area set for DRAM to 1 automatically inserts from 0 to 3 wait states, as set by WCRH and WCRL, between the Tc1 state and Tc2 state.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 7 Bus Controller (2) Insertion of Pin Waits When the WAITE bit of BCRH is set to 1, wait input via the WAIT pin is valid regardless of the ASTCR AST bit. In this state, a program wait is inserted when the DRAM space is accessed. If the WAIT pin level is Low at the fall in φ in the final Tc1 or Tw state, a further Tw is inserted. If the level of the WAIT pin is kept Low, Tw is inserted until the level of the WAIT pin changes to High.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 7.5.9 Section 7 Bus Controller Byte Access Control When 16-bit DRAMs are connected, the 2 CAS method can be used as the control signal required for byte access. Figure 7.19 shows the 2 CAS method control timing. Figure 7.20 shows an example of connecting DRAM in high-speed page mode. When all areas selected as DRAM space are set as 8-bit space, the LCAS pin functions as an I/O port.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 7 Bus Controller This LSI (address shift set to 9 bits) CS (RAS) 2CAS 4-Mbit DRAM 256 kbytes × 16-bit configuration 9-bit column address RAS CAS UCAS LCAS LCAS HWR (WE) WE A9 A8 A8 A7 A7 A6 A6 A5 (Column address input: A8 to A0) A5 A4 A4 A3 A3 A2 A2 A1 A1 A0 D15 to D0 (Row address input: A8 to A0) D15 to D0 OE Figure 7.20 High-speed Page Mode DRAM Page 220 of 1434 R01UH0166EJ0600 Rev. 6.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 7 Bus Controller This LSI (address shift set to 10 bits) CS2 (RAS) RAS CAS UCAS LCAS LCAS HWR (WE) A10 CS3 (OE) 2CAS 16-Mbit DRAM 1 Mbyte × 16-bit configuration 10-bit column address WE A9 A9 A8 A8 A7 A7 A6 A6 (Row address input: A9 to A0) A5 (Column address input: A9 to A0) A5 A4 A4 A3 A3 A2 A2 A1 A1 A0 D15 to D0 D15 to D0 OE Figure 7.21 Example Connection of EDO Page Mode DRAM (OES=1) 7.5.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 7 Bus Controller (1) Operation Timing for Burst Access (High-Speed Page Mode) Figure 7.22 shows the operation timing for burst access. When the DRAM space is successively accessed, the CAS signal and column address output cycle (2 states) are continued as long as the row address is the same in the preceding and succeeding access cycles. The MXC1 and MXC0 bits of the MCR specify which row address is compared.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 7 Bus Controller (2) RAS Down Mode and RAS Up Mode Even when burst operation is selected, DRAM access may not be continuous, but may be interrupted by accessing another area. In this case, burst operation can be continued by keeping the RAS signal level Low while the other area is accessed and then accessing the same row address in the DRAM space. • RAS down mode To select RAS down mode, set the RCDM bit of the MCR to 1.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 7 Bus Controller • RAS up mode To select RAS up mode, clear the RCDM bit of the MCR to 0. If DRAM access is interrupted to access another area, the RAS signal level returns to High. Burst operation is only possible when the DRAM space is contiguous. Figure 7.24 shows example timing in RAS up mode. Note that the RAS signal level does not return to High in burst ROM space access.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 7.5.11 Section 7 Bus Controller Refresh Control This LSI has a DRAM refresh control function. There are two refresh methods: (1) CAS-beforeRAS (CBR) and (2), self refresh. (1) CAS-Before-RAS (CBR) Refresh To select CBR refresh, set the RFSHE bit of DRAMCR to 1 and clear the RMODE bit to 0. In CBR refresh, the input clock selected with the CKS2 to CKS0 bits of DRAMCR are used for the RTCNT count-up.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 7 Bus Controller φ RTCNT N H'00 RTCOR N Refresh request signal and CMF bit setting signal Figure 7.26 Compare Match Timing Read access of normal space Write access of normal space φ A23 to A0 CS AS RD HWR (WE) Refresh cycle RAS CAS Figure 7.27 Example CBR Refresh Timing (CBRM=0) Page 226 of 1434 R01UH0166EJ0600 Rev. 6.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 7 Bus Controller Normal space access request φ A23 to A0 CS AS RD HWR (WE) Refresh cycle RAS CAS Figure 7.28 Example CBR Refresh Timing (CBRM=1) R01UH0166EJ0600 Rev. 6.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 7 Bus Controller (2) Self-Refresh One of the DRAM standby modes is the self-refresh mode (battery backup mode), in which the DRAM generates its own refresh timing and refresh address. To select self-refresh, set the RFSHE bit and RMODE bits of the DRAMCR to 1. Next, execute a SLEEP instruction to make a transition to software standby mode. As shown in figure 7.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 7.6 Section 7 Bus Controller DMAC Single Address Mode and DRAM Interface (This function is not available in the H8S/2695) When burst mode is set for the DRAM interface, the DDS bit selects the output timing for the DACK signal. It also selects whether or not to perform burst access when accessing the DRAM space in DMAC single address mode. 7.6.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 7 Bus Controller 7.6.2 DDS=0 When the DRAM space is accessed in DMAC single address mode, always perform full access (normal access). The DACK output level changes to Low afer the Tr state in the case of the DRAM interface. In other than DMAC signle address mode, burst access is possible when the DRAM space is accessed. Figure 7.31 shows the DACK output timing for the DRAM interface when DDS = 0.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 7.7 Burst ROM Interface 7.7.1 Overview Section 7 Bus Controller In this LSI, the area 0 external space can be set as burst ROM space and burst ROM interfacing performed. Burst ROM space interfacing allows 16-bit ROM capable of burst access to be accessed at high-speed. The BRSTRM bit of BCRH sets area 0 as burst ROM space. CPU instruction fetches (only) can be performed using a maximum of 4-word or 8-word continuous burst access.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 7 Bus Controller Full access T1 T2 Burst access T3 T1 T2 T1 T2 φ Low address only changes Address bus CS0 AS RD Data bus Read data Read data Read data Figure 7.32 (a) Example Burst ROM Access Timing (AST0=BRSTS1=1) Page 232 of 1434 R01UH0166EJ0600 Rev. 6.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 7 Bus Controller Full access T1 T2 Burst access T1 T1 φ Low address only changes Address bus CS0 AS RD Data bus Read data Read data Read data Figure 7.32 (b) Example Burst ROM Access Timing (AST0=BRSTS1=0) 7.7.3 Wait Control As with the basic bus interface, either program wait insertion or pin wait insertion using the WAIT pin can be used in the initial cycle (full access) of the burst ROM interface. See section 7.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 7 Bus Controller 7.8 Idle Cycle 7.8.1 Operation When the H8S/2633 Group accesses external space, it can insert a 1-state idle cycle (TI) between bus cycles in the following two cases: (1) when read accesses between different areas occur consecutively, and (2) when a write cycle occurs immediately after a read cycle.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 7 Bus Controller (2) Write after Read If an external write occurs after an external read while the ICIS0 bit in BCRH is set to 1, an idle cycle is inserted at the start of the write cycle. Figure 7.34 shows an example of the operation in this case. In this example, bus cycle A is a read cycle from ROM with a long output floating time, and bus cycle B is a CPU write cycle.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 7 Bus Controller (3) Relationship between Chip Select (CS) Signal and Read (RD) Signal Depending on the system’s load conditions, the RD signal may lag behind the CS signal. An example is shown in figure 7.35. In this case, with the setting for no idle cycle insertion (a), there may be a period of overlap between the bus cycle A RD signal and the bus cycle B CS signal.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 7 Bus Controller (4) Notes The setting of the ICIS0 and ICIS1 bits is invalid when accessing the DRAM space. For example, if the 2nd of successive reads of different areas is a DRAM access, only the TP cycle is inserted, not the T1 cycle. Figure 7.36 shows the timing. Note, however, that ICIS0 and ICIS1 settings are valid in burst access in RAS down mode, and an idle cycle is inserted. Figures 7.37 (a) and (b) show the timing.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 7 Bus Controller External read DRAM space read Tp Tr Tc1 Tc2 T1 T1 T2 DRAM space read T3 Tc1 Tc1 Tc2 EXTAL Address RD HWR RAS CAS, LCAS Data bus Idle cycle Figure 7.37 (b) Example Idle Cycle Operation in RAS Down Mode (ICIS0=1) 7.8.2 Pin States in Idle Cycle Table 7.8 shows pin states in an idle cycle. Table 7.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 7.9 Section 7 Bus Controller Write Data Buffer Function The H8S/2633 Group has a write data buffer function in the external data bus. Using the write data buffer function enables external writes and DMA single address mode transmission to be executed in parallel with internal accesses. The write data buffer function is made available by setting the WDBE bit in BCRL to 1. Figure 7.
Section 7 Bus Controller 7.10 Bus Release 7.10.1 Overview H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 The H8S/2633 Group can release the external bus in response to a bus request from an external device. In the external bus released state, the internal bus master continues to operate as long as there is no external access.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 7.10.3 Section 7 Bus Controller Pin States in External Bus Released State Table 7.9 shows pin states in the external bus released state. Table 7.9 Pins Pin States in Bus Released State Pin State A23 to A0 High impedance D15 to D0 High impedance CSn High impedance CAS High impedance AS High impedance RD High impedance HWR High impedance LWR High impedance DACKn High R01UH0166EJ0600 Rev. 6.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 7 Bus Controller 7.10.4 Transition Timing Figure 7.39 shows the timing for transition to the bus-released state. CPU cycle T0 T1 CPU cycle External bus released state T2 φ High impedance Address bus Address High impedance Data bus High impedance CSn High impedance AS High impedance RD High impedance HWR, LWR BREQ BACK BREQO* Minimum 1 state [1] [2] [3] [1] Low level of BREQ pin is sampled at rise of T2 state.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 7 Bus Controller DRAM space read access External bus released φ A23 to A0 CS AS RD RAS CAS BREQ BACK Figure 7.40 Example Bus Release Transition Timing After DRAM Access (Reading DRAM) 7.10.5 Notes The external bus release function is deactivated when MSTPCR is set to H'FFFFFF or H'EFFFFF and a transition is made to sleep mode.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 7 Bus Controller 7.11 Bus Arbitration (DMAC and DTC functions are not available in the H8S/2695) 7.11.1 Overview The H8S/2633 Group has a bus arbiter that arbitrates bus master operations. There are two bus masters, the CPU, DTC, and DMAC which perform read/write operations when they have possession of the bus. Each bus master requests the bus by means of a bus request signal.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 7.11.3 Section 7 Bus Controller Bus Transfer Timing Even if a bus request is received from a bus master with a higher priority than that of the bus master that has acquired the bus and is currently operating, the bus is not necessarily transferred immediately. There are specific times at which each bus master can relinquish the bus.
Section 7 Bus Controller Page 246 of 1434 H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 R01UH0166EJ0600 Rev. 6.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 8 DMA Controller (DMAC) (This function is not available in the H8S/2695) Section 8 DMA Controller (DMAC) (This function is not available in the H8S/2695) 8.1 Overview The H8S/2633 Group has a built-in DMA controller (DMAC) which can carry out data transfer on up to 4 channels. 8.1.1 Features The features of the DMAC are listed below.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 8 DMA Controller (DMAC) (This function is not available in the H8S/2695) • Module stop mode can be set ⎯ The initial setting enables DMAC registers to be accessed. DMAC operation is halted by setting module stop mode 8.1.2 Block Diagram A block diagram of the DMAC is shown in figure 8.1.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 8.1.3 Section 8 DMA Controller (DMAC) (This function is not available in the H8S/2695) Overview of Functions Tables 8.1 (1) and (2) summarize DMAC functions in short address mode and full address mode, respectively. Table 8.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 8 DMA Controller (DMAC) (This function is not available in the H8S/2695) Table 8.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 8.1.4 Section 8 DMA Controller (DMAC) (This function is not available in the H8S/2695) Pin Configuration Table 8.2 summarizes the DMAC pins. In short address mode, external request transfer, single address transfer, and transfer end output are not performed for channel A. The DMA transfer acknowledge function is used in channel B single address mode in short address mode.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 8 DMA Controller (DMAC) (This function is not available in the H8S/2695) 8.1.5 Register Configuration Table 8.3 summarizes the DMAC registers. Table 8.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 8.2 Section 8 DMA Controller (DMAC) (This function is not available in the H8S/2695) Register Descriptions (1) (Short Address Mode) Short address mode transfer can be performed for channels A and B independently. Short address mode transfer is specified for each channel by clearing the FAE bit in DMABCR to 0, as shown in table 8.4.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 8 DMA Controller (DMAC) (This function is not available in the H8S/2695) 8.2.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 8.2.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 8 DMA Controller (DMAC) (This function is not available in the H8S/2695) 8.2.3 Execute Transfer Count Register (ETCR) ETCR is a 16-bit readable/writable register that specifies the number of transfers. The setting of this register is different for sequential mode and idle mode on the one hand, and for repeat mode on the other.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 8 DMA Controller (DMAC) (This function is not available in the H8S/2695) (2) Repeat Mode Transfer Number Storage Bit : ETCRH : 15 Initial value : R/W : 14 13 12 11 10 9 8 * * * * * * * * R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 * * * * * * * * R/W R/W R/W R/W R/W R/W R/W R/W Transfer Counter Bit : ETCRL : Initial value : R/W : *: Undefined In repeat mode, ETCR fu
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 8 DMA Controller (DMAC) (This function is not available in the H8S/2695) 8.2.4 DMA Control Register (DMACR) Bit : 7 6 5 4 3 2 1 0 DMACR : DTSZ DTID RPE DTDIR DTF3 DTF2 DTF1 DTF0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Initial value : R/W : DMACR is an 8-bit readable/writable register that controls the operation of each DMAC channel.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 8 DMA Controller (DMAC) (This function is not available in the H8S/2695) Bit 5—Repeat Enable (RPE): Used in combination with the DTIE bit in DMABCR to select the mode (sequential, idle, or repeat) in which transfer is to be performed.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 8 DMA Controller (DMAC) (This function is not available in the H8S/2695) Bits 3 to 0—Data Transfer Factor (DTF3 to DTF0): These bits select the data transfer factor (activation source). There are some differences in activation sources for channel A and for channel B.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 8 DMA Controller (DMAC) (This function is not available in the H8S/2695) Channel B Bit 3 Bit 2 Bit 1 Bit 0 DTF3 DTF2 DTF1 DTF0 Description 0 0 0 0 — 1 0 Activated by A/D converter conversion end interrupt Activated by DREQ pin falling edge input* 1 Activated by DREQ pin low-level input 0 Activated by SCI channel 0 transmit-data-empty interrupt 1 Activated by SCI channel 0 reception complete interrupt 0 Acti
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 8 DMA Controller (DMAC) (This function is not available in the H8S/2695) 8.2.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 8 DMA Controller (DMAC) (This function is not available in the H8S/2695) Bit 13—Single Address Enable 1 (SAE1): Specifies whether channel 1B is to be used for transfer in dual address mode or single address mode. Bit 13 SAE1 Description 0 Transfer in dual address mode 1 Transfer in single address mode (Initial value) This bit is invalid in full address mode.
Section 8 DMA Controller (DMAC) (This function is not available in the H8S/2695) H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Bit 11—Data Transfer Acknowledge 1B (DTA1B): Enables or disables clearing, when DMA transfer is performed, of the internal interrupt source selected by the channel 1B data transfer factor setting.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 8 DMA Controller (DMAC) (This function is not available in the H8S/2695) Bit 8—Data Transfer Acknowledge 0A (DTA0A): Enables or disables clearing, when DMA transfer is performed, of the internal interrupt source selected by the channel 0A data transfer factor setting.
Section 8 DMA Controller (DMAC) (This function is not available in the H8S/2695) H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Bit 6—Data Transfer Enable 1A (DTE1A): Enables or disables data transfer on channel 1A. Bit 6 DTE1A Description 0 Data transfer disabled 1 Data transfer enabled (Initial value) Bit 5—Data Transfer Enable 0B (DTE0B): Enables or disables data transfer on channel 0B.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 8 DMA Controller (DMAC) (This function is not available in the H8S/2695) Bit 3—Data Transfer End Interrupt Enable 1B (DTIE1B): Enables or disables the channel 1B transfer end interrupt. Bit 3 DTIE1B Description 0 Transfer end interrupt disabled 1 Transfer end interrupt enabled (Initial value) Bit 2—Data Transfer End Interrupt Enable 1A (DTIE1A): Enables or disables the channel 1A transfer end interrupt.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 8 DMA Controller (DMAC) (This function is not available in the H8S/2695) 8.3 Register Descriptions (2) (Full Address Mode) Full address mode transfer is performed with channels A and B together. For details of full address mode setting, see table 8.4. 8.3.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 8.3.3 Section 8 DMA Controller (DMAC) (This function is not available in the H8S/2695) Execute Transfer Count Register (ETCR) ETCR is a 16-bit readable/writable register that specifies the number of transfers. The function of this register is different in normal mode and in block transfer mode. ETCR is not initialized by a reset or in standby mode.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 8 DMA Controller (DMAC) (This function is not available in the H8S/2695) (2) Block Transfer Mode ETCRA Holds block size Bit : ETCRAH : 15 14 13 12 11 10 9 8 * * * * * * * * R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 * * * * * * * * R/W R/W R/W R/W R/W R/W R/W R/W Initial value : R/W : Block size counter Bit : ETCRAL : Initial value : R/W : *: Undefined ETCRB Block Tra
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 8.3.4 Section 8 DMA Controller (DMAC) (This function is not available in the H8S/2695) DMA Control Register (DMACR) DMACR is a 16-bit readable/writable register that controls the operation of each DMAC channel. In full address mode, DMACRA and DMACRB have different functions. DMACR is initialized to H'0000 by a reset, and in standby mode.
Section 8 DMA Controller (DMAC) (This function is not available in the H8S/2695) H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Bit 13—Source Address Increment/Decrement Enable (SAIDE): These bits specify whether source address register MARA is to be incremented, decremented, or left unchanged, when data transfer is performed.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 8 DMA Controller (DMAC) (This function is not available in the H8S/2695) Bit 5—Destination Address Increment/Decrement Enable (DAIDE): These bits specify whether destination address register MARB is to be incremented, decremented, or left unchanged, when data transfer is performed.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 8 DMA Controller (DMAC) (This function is not available in the H8S/2695) • Block Transfer Mode Bit 3 Bit 2 Bit 1 Bit 0 DTF3 DTF2 DTF1 DTF0 Description 0 0 0 0 — 1 0 Activated by A/D converter conversion end interrupt Activated by DREQ pin falling edge input* 1 Activated by DREQ pin low-level input 0 Activated by SCI channel 0 transmit-data-empty interrupt 1 Activated by SCI channel 0 reception complete interrupt
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 8.3.
Section 8 DMA Controller (DMAC) (This function is not available in the H8S/2695) H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Bits 13 and 12—Reserved: Can be read or written to. Bits 11 and 9—Data Transfer Acknowledge (DTA): These bits enable or disable clearing, when DMA transfer is performed, of the internal interrupt source selected by the data transfer factor setting.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 8 DMA Controller (DMAC) (This function is not available in the H8S/2695) Bits 10 and 8—Reserved: Can be read or written to. Bits 7 and 5—Data Transfer Master Enable (DTME): Together with the DTE bit, these bits control enabling or disabling of data transfer on the relevant channel. When both the DTME bit and the DTE bit are set to 1, transfer is enabled for the channel.
Section 8 DMA Controller (DMAC) (This function is not available in the H8S/2695) H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Bits 6 and 4—Data Transfer Enable (DTE): When DTE = 0, data transfer is disabled and the activation source selected by the data transfer factor setting is ignored. If the activation source is an internal interrupt, an interrupt request is issued to the CPU or DTC.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 8 DMA Controller (DMAC) (This function is not available in the H8S/2695) A transfer break interrupt can be canceled either by clearing the DTIEB bit to 0 in the interrupt handling routine, or by performing processing to continue transfer by setting the DTME bit to 1. Bit 3—Data Transfer Interrupt Enable 1B (DTIE1B): Enables or disables the channel 1 transfer break interrupt.
Section 8 DMA Controller (DMAC) (This function is not available in the H8S/2695) H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Bit 0—Data Transfer End Interrupt Enable 0A (DTIE0A): Enables or disables the channel 0 transfer end interrupt. Bit 0 DTIE0A Description 0 Transfer end interrupt disabled 1 Transfer end interrupt enabled 8.4 Register Descriptions (3) 8.4.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 8 DMA Controller (DMAC) (This function is not available in the H8S/2695) MAR0A First transfer area IOAR0A ETCR0A MAR0B IOAR0B ETCR0B MAR1A DTC IOAR1A ETCR1A MAR1B IOAR1B ETCR1B DMAWER DMATCR DMACR0A DMACR0B DMACR1A DMACR1B Second transfer area using chain transfer DMABCR Figure 8.
Section 8 DMA Controller (DMAC) (This function is not available in the H8S/2695) H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Bit 3—Write Enable 1B (WE1B): Enables or disables writes to all bits in DMACR1B, bits 11, 7, and 3 in DMABCR, and bit 5 in DMATCR by the DTC.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 8 DMA Controller (DMAC) (This function is not available in the H8S/2695) Writes by the DTC to bits 15 to 12 (FAE and SAE) in DMABCR are invalid regardless of the DMAWER settings. These bits should be changed, if necessary, by CPU processing. In writes by the DTC to bits 7 to 4 (DTE) in DMABCR, 1 can be written without first reading 0.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 8 DMA Controller (DMAC) (This function is not available in the H8S/2695) The TEND pins are assigned only to channel B in short address mode. The transfer end signal indicates the transfer cycle in which the transfer counter reached 0, regardless of the transfer source. An exception is block transfer mode, in which the transfer end signal indicates the transfer cycle in which the block counter reached 0.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 8.5 Operation 8.5.1 Transfer Modes Section 8 DMA Controller (DMAC) (This function is not available in the H8S/2695) Table 8.5 lists the DMAC modes. Table 8.
Section 8 DMA Controller (DMAC) (This function is not available in the H8S/2695) H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Operation in each mode is summarized below. (1) Sequential mode In response to a single transfer request, the specified number of transfers are carried out, one byte or one word at a time. An interrupt request can be sent to the CPU or DTC when the specified number of transfers have been completed. One address is specified as 24 bits, and the other as 16 bits.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 8 DMA Controller (DMAC) (This function is not available in the H8S/2695) • External request In response to a single transfer request, the specified number of transfers are carried out, one byte or one word at a time. An interrupt request can be sent to the CPU or DTC when the specified number of transfers have been completed. Both addresses are specified as 24 bits.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 8 DMA Controller (DMAC) (This function is not available in the H8S/2695) MAR specifies the start address of the transfer source or transfer destination as 24 bits. MAR is incremented or decremented by 1 or 2 each time a byte or word is transferred. IOAR specifies the lower 16 bits of the other address. The 8 bits above IOAR have a value of H'FF. Figure 8.3 illustrates operation in sequential mode.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 8 DMA Controller (DMAC) (This function is not available in the H8S/2695) Transfer requests (activation sources) consist of A/D converter conversion end interrupts, external requests, SCI transmission complete and reception complete interrupts, and TPU channels 0 to 5 compare match/input capture A interrupts. External requests can be set for channel B only. Figure 8.4 shows an example of the setting procedure for sequential mode.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 8 DMA Controller (DMAC) (This function is not available in the H8S/2695) 8.5.3 Idle Mode Idle mode can be specified by setting the RPE bit and DTIE bit in DMACR to 1. In idle mode, one byte or word is transferred in response to a single transfer request, and this is executed the number of times specified in ETCR. One address is specified by MAR, and the other by IOAR.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 8 DMA Controller (DMAC) (This function is not available in the H8S/2695) Figure 8.5 illustrates operation in idle mode. MAR Transfer IOAR 1 byte or word transfer performed in response to 1 transfer request Figure 8.5 Operation in Idle Mode The number of transfers is specified as 16 bits in ETCR.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 8 DMA Controller (DMAC) (This function is not available in the H8S/2695) Figure 8.6 shows an example of the setting procedure for idle mode. [1] Set each bit in DMABCRH. • Clear the FAE bit to 0 to select short address mode. • Specify enabling or disabling of internal interrupt clearing with the DTA bit. Idle mode setting Set DMABCRH [1] [2] Set the transfer source address and transfer destination address in MAR and IOAR.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 8.5.4 Section 8 DMA Controller (DMAC) (This function is not available in the H8S/2695) Repeat Mode Repeat mode can be specified by setting the RPE bit in DMACR to 1, and clearing the DTIE bit to 0. In repeat mode, MAR is updated after each byte or word transfer in response to a single transfer request, and this is executed the number of times specified in ETCR.
Section 8 DMA Controller (DMAC) (This function is not available in the H8S/2695) H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 MAR specifies the start address of the transfer source or transfer destination as 24 bits. MAR is incremented or decremented by 1 or 2 each time a byte or word is transferred. IOAR specifies the lower 16 bits of the other address. The 8 bits above IOAR have a value of H'FF. The number of transfers is specified as 8 bits by ETCRH and ETCRL.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 8 DMA Controller (DMAC) (This function is not available in the H8S/2695) Figure 8.7 illustrates operation in repeat mode. Address T Transfer IOAR 1 byte or word transfer performed in response to 1 transfer request Address B Legend: Address T = L Address B = L + (–1)DTID · (2DTSZ · (N–1)) Where: L = Value set in MAR N = Value set in ETCR Figure 8.
Section 8 DMA Controller (DMAC) (This function is not available in the H8S/2695) H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Figure 8.8 shows an example of the setting procedure for repeat mode. [1] Set each bit in DMABCRH. • Clear the FAE bit to 0 to select short address mode. • Specify enabling or disabling of internal interrupt clearing with the DTA bit. Repeat mode setting Set DMABCRH [1] [2] Set the transfer source address and transfer destination address in MAR and IOAR.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 8.5.5 Section 8 DMA Controller (DMAC) (This function is not available in the H8S/2695) Single Address Mode Single address mode can only be specified for channel B. This mode can be specified by setting the SAE bit in DMABCR to 1 in short address mode. One address is specified by MAR, and the other is set automatically to the data transfer acknowledge pin (DACK). The transfer direction can be specified by the DTDIR in DMACR. Table 8.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 8 DMA Controller (DMAC) (This function is not available in the H8S/2695) Figure 8.9 illustrates operation in single address mode (when sequential mode is specified). Address T DACK Transfer 1 byte or word transfer performed in response to 1 transfer request Address B Legend: Address T = L Address B = L + (–1)DTID · (2DTSZ · (N–1)) Where: L = Value set in MAR N = Value set in ETCR Figure 8.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 8 DMA Controller (DMAC) (This function is not available in the H8S/2695) Figure 8.10 shows an example of the setting procedure for single address mode (when sequential mode is specified). Single address mode setting Set DMABCRH Set transfer source and transfer destination addresses [1] [1] Set each bit in DMABCRH. • Clear the FAE bit to 0 to select short address mode. • Set the SAE bit to 1 to select single address mode.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 8 DMA Controller (DMAC) (This function is not available in the H8S/2695) 8.5.6 Normal Mode In normal mode, transfer is performed with channels A and B used in combination. Normal mode can be specified by setting the FAE bit in DMABCR to 1 and clearing the BLKE bit in DMACRA to 0.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 8 DMA Controller (DMAC) (This function is not available in the H8S/2695) Figure 8.11 illustrates operation in normal mode. Transfer Address TA Address BB Address BA Legend: Address Address Address Address Where: TA TB BA BB LA LB N Address TB = LA = LB = LA + SAIDE · (–1)SAID · (2DTSZ · (N–1)) = LB + DAIDE · (–1)DAID · (2DTSZ · (N–1)) = Value set in MARA = Value set in MARB = Value set in ETCRA Figure 8.
Section 8 DMA Controller (DMAC) (This function is not available in the H8S/2695) H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 For setting details, see section 8.3.4, DMA Controller Register (DMACR). Figure 8.12 shows an example of the setting procedure for normal mode. [1] Set each bit in DMABCRH. • Set the FAE bit to 1 to select full address mode. • Specify enabling or disabling of internal interrupt clearing with the DTA bit.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 8.5.7 Section 8 DMA Controller (DMAC) (This function is not available in the H8S/2695) Block Transfer Mode In block transfer mode, transfer is performed with channels A and B used in combination. Block transfer mode can be specified by setting the FAE bit in DMABCR and the BLKE bit in DMACRA to 1.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 8 DMA Controller (DMAC) (This function is not available in the H8S/2695) Incrementing, decrementing, or holding a fixed value can be set separately for MARA and MARB. Whether a block is to be designated for MARA or for MARB is specified by the BLKDIR bit in DMACRA.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 8 DMA Controller (DMAC) (This function is not available in the H8S/2695) Figure 8.14 illustrates operation in block transfer mode when MARA is designated as a block area.
Section 8 DMA Controller (DMAC) (This function is not available in the H8S/2695) H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 ETCRAL is decremented by 1 each time a byte or word transfer is performed. In response to a single transfer request, burst transfer is performed until the value in ETCRAL reaches H'00. ETCRAL is then loaded with the value in ETCRAH.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 8 DMA Controller (DMAC) (This function is not available in the H8S/2695) Start (DTE = DTME = 1) Transfer request? No Yes Acquire bus Read address specified by MARA MARA=MARA+SAIDE·(–1)SAID·2DTSZ Write to address specified by MARB MARB=MARB+DAIDE·(–1)DAID ·2DTSZ ETCRAL=ETCRAL–1 ETCRAL=H'00 No Yes Release bus ETCRAL=ETCRAH BLKDIR=0 No Yes MARB=MARB–DAIDE·(–1)DAID·2DTSZ·ETCRAH MARA=MARA–SAIDE·(–1)SAID·2DTSZ·ETCRAH ETCRB=ET
Section 8 DMA Controller (DMAC) (This function is not available in the H8S/2695) H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Figure 8.16 shows an example of the setting procedure for block transfer mode. [1] Set each bit in DMABCRH. • Set the FAE bit to 1 to select full address mode. • Specify enabling or disabling of internal interrupt clearing with the DTA bit.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 8.5.8 Section 8 DMA Controller (DMAC) (This function is not available in the H8S/2695) DMAC Activation Sources DMAC activation sources consist of internal interrupts, external requests, and auto-requests. The activation sources that can be specified depend on the transfer mode and the channel, as shown in table 8.12. Table 8.
Section 8 DMA Controller (DMAC) (This function is not available in the H8S/2695) H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 unless the prescribed register is accessed in a DMA transfer. If the same interrupt is used as an activation source for more than one channel, the interrupt request flag is cleared when the highestpriority channel is activated first. Transfer requests for other channels are held pending in the DMAC, and activation is carried out in order of priority.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 8 DMA Controller (DMAC) (This function is not available in the H8S/2695) In dual address mode, transfer is performed with the source address and destination address specified separately.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 8 DMA Controller (DMAC) (This function is not available in the H8S/2695) 8.5.9 Basic DMAC Bus Cycles An example of the basic DMAC bus cycle timing is shown in figure 8.18. In this example, wordsize transfer is performed from 16-bit , 2-state access space to 8-bit, 3-state access space. When the bus is transferred from the CPU to the DMAC, a source address read and destination address write are performed.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 8.5.10 Section 8 DMA Controller (DMAC) (This function is not available in the H8S/2695) DMAC Bus Cycles (Dual Address Mode) Short Address Mode: Figure 8.19 shows a transfer example in which TEND output is enabled and byte-size short address mode transfer (sequential/idle/repeat mode) is performed from external 8-bit, 2-state access space to internal I/O space.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 8 DMA Controller (DMAC) (This function is not available in the H8S/2695) Full Address Mode (Cycle Steal Mode): Figure 8.20 shows a transfer example in which TEND output is enabled and word-size full address mode transfer (cycle steal mode) is performed from external 16-bit, 2-state access space to external 16-bit, 2-state access space.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 8 DMA Controller (DMAC) (This function is not available in the H8S/2695) Full Address Mode (Burst Mode): Figure 8.21 shows a transfer example in which TEND output is enabled and word-size full address mode transfer (burst mode) is performed from external 16bit, 2-state access space to external 16-bit, 2-state access space.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 8 DMA Controller (DMAC) (This function is not available in the H8S/2695) Full Address Mode (Block Transfer Mode): Figure 8.22 shows a transfer example in which TEND output is enabled and word-size full address mode transfer (block transfer mode) is performed from internal 16-bit, 1-state access space to external 16-bit, 2-state access space.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 8 DMA Controller (DMAC) (This function is not available in the H8S/2695) DREQ Pin Falling Edge Activation Timing: Set the DTA bit for the channel for which the DREQ pin is selected to 1. Figure 8.23 shows an example of DREQ pin falling edge activated normal mode transfer.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 8 DMA Controller (DMAC) (This function is not available in the H8S/2695) Figure 8.24 shows an example of DREQ pin falling edge activated block transfer mode transfer.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 8 DMA Controller (DMAC) (This function is not available in the H8S/2695) DREQ Level Activation Timing (Normal Mode): Set the DTA bit for the channel for which the DREQ pin is selected to 1. Figure 8.25 shows an example of DREQ level activated normal mode transfer.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 8 DMA Controller (DMAC) (This function is not available in the H8S/2695) Figure 8.26 shows an example of DREQ level activated block transfer mode transfer.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 8.5.11 Section 8 DMA Controller (DMAC) (This function is not available in the H8S/2695) DMAC Bus Cycles (Single Address Mode) Single Address Mode (Read): Figure 8.27 shows a transfer example in which TEND output is enabled and byte-size single address mode transfer (read) is performed from external 8-bit, 2-state access space to an external device.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 8 DMA Controller (DMAC) (This function is not available in the H8S/2695) Figure 8.28 shows a transfer example in which TEND output is enabled and word-size single address mode transfer (read) is performed from external 8-bit, 2-state access space to an external device. DMA read DMA read DMA read DMA dead φ Address bus RD DACK TEND Bus release Bus release Bus release Last transfer cycle Bus release Figure 8.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 8 DMA Controller (DMAC) (This function is not available in the H8S/2695) Single Address Mode (Write): Figure 8.29 shows a transfer example in which TEND output is enabled and byte-size single address mode transfer (write) is performed from an external device to external 8-bit, 2-state access space.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 8 DMA Controller (DMAC) (This function is not available in the H8S/2695) Figure 8.30 shows a transfer example in which TEND output is enabled and word-size single address mode transfer (write) is performed from an external device to external 8-bit, 2-state access space. DMA write DMA write DMA write DMA dead φ Address bus HWR LWR DACK TEND Bus release Bus release Bus release Last transfer cycle Bus release Figure 8.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 8 DMA Controller (DMAC) (This function is not available in the H8S/2695) DREQ Pin Falling Edge Activation Timing: Set the DTA bit for the channel for which the DREQ pin is selected to 1. Figure 8.31 shows an example of DREQ pin falling edge activated single address mode transfer.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 8 DMA Controller (DMAC) (This function is not available in the H8S/2695) DREQ Pin Low Level Activation Timing: Set the DTA bit for the channel for which the DREQ pin is selected to 1. Figure 8.32 shows an example of DREQ pin low level activated single address mode transfer.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 8.5.12 Section 8 DMA Controller (DMAC) (This function is not available in the H8S/2695) Write Data Buffer Function DMAC internal-to-external dual address transfers and single address transfers can be executed at high speed using the write data buffer function, enabling system throughput to be improved.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 8 DMA Controller (DMAC) (This function is not available in the H8S/2695) DMA read DMA single CPU read DMA single CPU read φ Internal address Internal read signal External address RD DACK Figure 8.34 Example of Single Address Transfer Using Write Data Buffer Function When the write data buffer function is activated, the DMAC recognizes that the bus cycle concerned has ended, and starts the next operation.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 8 DMA Controller (DMAC) (This function is not available in the H8S/2695) If transfer requests are issued simultaneously for more than one channel, or if a transfer request for another channel is issued during a transfer, when the bus is released the DMAC selects the highest-priority channel from among those issuing a request according to the priority order shown in table 8.13.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 8 DMA Controller (DMAC) (This function is not available in the H8S/2695) When DMA cycle reads or writes are accesses to on-chip memory or internal I/O registers, these DMA cycles can be executed at the same time as refresh cycles or external bus release. However, simultaneous operation may not be possible when a write buffer is used. 8.5.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 8.5.16 Section 8 DMA Controller (DMAC) (This function is not available in the H8S/2695) Forced Termination of DMAC Operation If the DTE bit for the channel currently operating is cleared to 0, the DMAC stops on completion of the 1-byte or 1-word transfer in progress. DMAC operation resumes when the DTE bit is set to 1 again. In full address mode, the same applies to the DTME bit. Figure 8.
Section 8 DMA Controller (DMAC) (This function is not available in the H8S/2695) 8.5.17 H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Clearing Full Address Mode Figure 8.38 shows the procedure for releasing and initializing a channel designated for full address mode. After full address mode has been cleared, the channel can be set to another transfer mode using the appropriate setting procedure.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 8.6 Section 8 DMA Controller (DMAC) (This function is not available in the H8S/2695) Interrupts The sources of interrupts generated by the DMAC are transfer end and transfer break. Table 8.14 shows the interrupt sources and their priority order. Table 8.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 8 DMA Controller (DMAC) (This function is not available in the H8S/2695) 8.7 Usage Notes DMAC Register Access during Operation: Except for forced termination, the operating (including transfer waiting state) channel setting should not be changed. The operating channel setting should only be changed when transfer is disabled. Also, the DMAC register should not be written to in a DMA transfer.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 8 DMA Controller (DMAC) (This function is not available in the H8S/2695) (b) If a DMAC transfer cycle occurs immediately after a DMAC register read cycle, the DMAC register is read as shown in figure 8.41.
Section 8 DMA Controller (DMAC) (This function is not available in the H8S/2695) H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Write Data Buffer Function: When the WDBE bit of BCRL in the bus controller is set to 1, enabling the write data buffer function, dual address transfer external write cycles or single address transfers and internal accesses (on-chip memory or internal I/O registers) are executed in parallel.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 8 DMA Controller (DMAC) (This function is not available in the H8S/2695) Figure 8.42 shows an example in which a low level is not output at the TEND pin. DMA read DMA write φ Internal address Internal read signal Internal write signal External address HWR, LWR TEND Not output External write by CPU, etc. Figure 8.
Section 8 DMA Controller (DMAC) (This function is not available in the H8S/2695) H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Activation Source Acceptance: At the start of activation source acceptance, a low level is detected in both DREQ pin falling edge sensing and low level sensing. Similarly, in the case of an internal interrupt, the interrupt request is detected.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 9 Data Transfer Controller (DTC) (This function is not available in the H8S/2695) Section 9 Data Transfer Controller (DTC) (This function is not available in the H8S/2695) 9.1 Overview The H8S/2633 Group includes a data transfer controller (DTC). The DTC can be activated by an interrupt or software, to transfer data. 9.1.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 9 Data Transfer Controller (DTC) (This function is not available in the H8S/2695) 9.1.2 Block Diagram Figure 9.1 shows a block diagram of the DTC. The DTC’s register information is stored in the on-chip RAM*. A 32-bit bus connects the DTC to the on-chip RAM (1 kbyte), enabling 32-bit/1-state reading and writing of the DTC register information. Note: * When the DTC is used, the RAME bit in SYSCR must be set to 1.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 9.1.3 Section 9 Data Transfer Controller (DTC) (This function is not available in the H8S/2695) Register Configuration Table 9.1 summarizes the DTC registers. Table 9.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 9 Data Transfer Controller (DTC) (This function is not available in the H8S/2695) 9.2 Register Descriptions 9.2.1 DTC Mode Register A (MRA) Bit : Initial value : R/W : 7 6 5 4 3 2 1 0 SM1 SM0 DM1 DM0 MD1 MD0 DTS Sz Undefined — Undefined — Undefined — Undefined — Undefined — Undefined — Undefined — Undefined — MRA is an 8-bit register that controls the DTC operating mode.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 9 Data Transfer Controller (DTC) (This function is not available in the H8S/2695) Bits 3 and 2—DTC Mode (MD1, MD0): These bits specify the DTC transfer mode.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 9 Data Transfer Controller (DTC) (This function is not available in the H8S/2695) Bit 7—DTC Chain Transfer Enable (CHNE): Specifies chain transfer. With chain transfer, a number of data transfers can be performed consecutively in response to a single transfer request.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 9.2.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 9 Data Transfer Controller (DTC) (This function is not available in the H8S/2695) 9.2.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 9 Data Transfer Controller (DTC) (This function is not available in the H8S/2695) A DTCE bit can be set for each interrupt source that can activate the DTC. The correspondence between interrupt sources and DTCE bits is shown in table 9.4, together with the vector number generated for each interrupt controller. For DTCE bit setting, use bit manipulation instructions such as BSET and BCLR for reading and writing.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 9 Data Transfer Controller (DTC) (This function is not available in the H8S/2695) Bits 6 to 0—DTC Software Activation Vectors 6 to 0 (DTVEC6 to DTVEC0): These bits specify a vector number for DTC software activation. The vector address is expressed as H'0400 + ((vector number) << 1). <<1 indicates a one-bit leftshift. For example, when DTVEC6 to DTVEC0 = H'10, the vector address is H'0420. 9.2.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 9.3 Operation 9.3.1 Overview Section 9 Data Transfer Controller (DTC) (This function is not available in the H8S/2695) When activated, the DTC reads register information that is already stored in memory and transfers data on the basis of that register information. After the data transfer, it writes updated register information back to memory.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 9 Data Transfer Controller (DTC) (This function is not available in the H8S/2695) The DTC transfer mode can be normal mode, repeat mode, or block transfer mode. The 24-bit SAR designates the DTC transfer source address and the 24-bit DAR designates the transfer destination address. After each transfer, SAR and DAR are independently incremented, decremented, or left fixed. Table 9.2 outlines the functions of the DTC. Table 9.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 9.3.2 Section 9 Data Transfer Controller (DTC) (This function is not available in the H8S/2695) Activation Sources The DTC operates when activated by an interrupt or by a write to DTVECR by software. An interrupt request can be directed to the CPU or DTC, as designated by the corresponding DTCER bit.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 9 Data Transfer Controller (DTC) (This function is not available in the H8S/2695) Source flag cleared Clear controller Clear DTCER Clear request On-chip supporting module IRQ interrupt DTVECR Interrupt request Selection circuit Select DTC Interrupt controller CPU Interrupt mask Figure 9.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 9.3.3 Section 9 Data Transfer Controller (DTC) (This function is not available in the H8S/2695) DTC Vector Table Figure 9.4 shows the correspondence between DTC vector addresses and register information. Table 9.4 shows the correspondence between activation and vector addresses. When the DTC is activated by software, the vector address is obtained from: H'0400 + (DTVECR[6:0] << 1) (where << 1 indicates a 1-bit left shift).
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 9 Data Transfer Controller (DTC) (This function is not available in the H8S/2695) Table 9.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 9 Data Transfer Controller (DTC) (This function is not available in the H8S/2695) Interrupt Source Origin of Interrupt Source TGI3A (GR3A compare match/ input capture) TPU channel 3 Vector Number Vector Address DTCE* Priority 48 H'0460 DTCEC5 High TGI3B (GR3B compare match/ input capture) 49 H'0462 DTCEC4 TGI3C (GR3C compare match/ input capture) 50 H'0464 DTCEC3 TGI3D (GR3D compare match/ input capture) 51
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 9 Data Transfer Controller (DTC) (This function is not available in the H8S/2695) Interrupt Source CMIA2 (compare match A2) CMIB2 (compare match B2) CMIA3 (compare match A3) CMIB3 (compare match B3) Origin of Interrupt Source 8-bit timer channel 2 8-bit timer channel 3 Vector Number Vector Address DTCE* Priority 92 H'04B8 DTCEF5 High 93 H'04BA DTCEF4 96 H'04C0 DTCEF3 97 H'04C2 DTCEF2 IICI0 (1-byte transmit/recepti
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 9.3.4 Section 9 Data Transfer Controller (DTC) (This function is not available in the H8S/2695) Location of Register Information in Address Space Figure 9.5 shows how the register information should be located in the address space. Locate the MRA, SAR, MRB, DAR, CRA, and CRB registers, in that order, from the start address of the register information (contents of the vector address).
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 9 Data Transfer Controller (DTC) (This function is not available in the H8S/2695) 9.3.5 Normal Mode In normal mode, one operation transfers one byte or one word of data. From 1 to 65,536 transfers can be specified. Once the specified number of transfers have ended, a CPU interrupt can be requested. Table 9.5 lists the register information in normal mode and figure 9.6 shows memory mapping in normal mode. Table 9.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 9.3.6 Section 9 Data Transfer Controller (DTC) (This function is not available in the H8S/2695) Repeat Mode In repeat mode, one operation transfers one byte or one word of data. From 1 to 256 transfers can be specified. Once the specified number of transfers have ended, the initial state of the transfer counter and the address register specified as the repeat area is restored, and transfer is repeated.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 9 Data Transfer Controller (DTC) (This function is not available in the H8S/2695) 9.3.7 Block Transfer Mode In block transfer mode, one operation transfers one block of data. Either the transfer source or the transfer destination is designated as a block area. The block size is 1 to 256.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 9 Data Transfer Controller (DTC) (This function is not available in the H8S/2695) First block · · · SAR or DAR Block area DAR or SAR Transfer Nth block Figure 9.8 Memory Mapping in Block Transfer Mode R01UH0166EJ0600 Rev. 6.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 9 Data Transfer Controller (DTC) (This function is not available in the H8S/2695) 9.3.8 Chain Transfer Setting the CHNE bit to 1 enables a number of data transfers to be performed consectutively in response to a single transfer request. SAR, DAR, CRA, CRB, MRA, and MRB, which define data transfers, can be set independently. Figure 9.9 shows the memory map for chain transfer.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 9.3.9 Section 9 Data Transfer Controller (DTC) (This function is not available in the H8S/2695) Operation Timing Figures 9.10 to 9.12 show an example of DTC operation timing. φ DTC activation request DTC request Data transfer Vector read Address Read Write Transfer information read Transfer information write Figure 9.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 9 Data Transfer Controller (DTC) (This function is not available in the H8S/2695) φ DTC activation request DTC request Data transfer Data transfer Read Write Read Write Vector read Address Transfer information read Transfer Transfer information information write read Transfer information write Figure 9.12 DTC Operation Timing (Example of Chain Transfer) 9.3.10 Number of DTC Execution States Table 9.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Table 9.
Section 9 Data Transfer Controller (DTC) (This function is not available in the H8S/2695) 9.3.11 H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Procedures for Using DTC Activation by Interrupt: The procedure for using the DTC with interrupt activation is as follows: [1] Set the MRA, MRB, SAR, DAR, CRA, and CRB register information in the on-chip RAM. [2] Set the start address of the register information in the DTC vector address. [3] Set the corresponding bit in DTCER to 1.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 9.3.12 Section 9 Data Transfer Controller (DTC) (This function is not available in the H8S/2695) Examples of Use of the DTC (1) Normal Mode An example is shown in which the DTC is used to receive 128 bytes of data via the SCI. [1] Set MRA to fixed source address (SM1 = SM0 = 0), incrementing destination address (DM1 = 1, DM0 = 0), normal mode (MD1 = MD0 = 0), and byte size (Sz = 0). The DTS bit can have any value.
Section 9 Data Transfer Controller (DTC) (This function is not available in the H8S/2695) H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 (2) Chain Transfer An example of DTC chain transfer is shown in which pulse output is performed using the PPG. Chain transfer can be used to perform pulse output data transfer and PPG output trigger cycle updating.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 9 Data Transfer Controller (DTC) (This function is not available in the H8S/2695) (3) Software Activation An example is shown in which the DTC is used to transfer a block of 128 bytes of data by means of software activation. The transfer source address is H'1000 and the destination address is H'2000. The vector number is H'60, so the vector address is H'04C0.
Section 9 Data Transfer Controller (DTC) (This function is not available in the H8S/2695) 9.4 H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Interrupts An interrupt request is issued to the CPU when the DTC finishes the specified number of data transfers, or a data transfer for which the DISEL bit was set to 1. In the case of interrupt activation, the interrupt set as the activation source is generated.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 10A I/O Ports (H8S/2633, H8S/2632, H8S/2631, H8S/2633R) Section 10A I/O Ports (H8S/2633, H8S/2632, H8S/2631, H8S/2633R) 10A.1 Overview The H8S/2633 Group has 10 I/O ports (ports 1, 3, 7 and A to G), and two input-only port (ports 4 and 9). Table 10A.1 summarizes the port functions. The pins of each port also have other functions.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 10A I/O Ports (H8S/2633, H8S/2632, H8S/2631, H8S/2633R) Table 10A.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Port Description Port 4 • 8-bit input port Pins P47 /AN7/DA1 P46 /AN6/DA0 Section 10A I/O Ports (H8S/2633, H8S/2632, H8S/2631, H8S/2633R) Mode 4 Mode 5 Mode 6 Mode 7 8-bit input port also functioning as A/D converter analog inputs (AN7 to AN0) and D/A converter analog outputs (DA1, DA0) P45 /AN5 P44 /AN4 P43 /AN3 P42 /AN2 P41 /AN1 P40/AN0 Port 7 • 8-bit I/O port P77/TxD3 P76/RxD3 P75/TMO3/SCK3 P74/TMO2/MRES P73/TMO1/TEND1/ CS7
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 10A I/O Ports (H8S/2633, H8S/2632, H8S/2631, H8S/2633R) Port Description Port A • 4-bit I/O port • Built-in MOS input pull-up Pins PA3/A19/SCK2 PA2/A18/RxD2 PA1/A17/TxD2 Mode 4 Mode 5 Mode 6 4-bit I/O port also functioning as SCI (channel 2) I/O pins (TxD2, RxD2, SCK2) and address outputs (A19 to A16) 4-bit I/O port also functioning as SCI (channel 2) I/O pins (TxD2, RxD2, SCK2) 8-bit I/O port also functioning as TPU I/O pi
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Port Description Port E • 8-bit I/O port • Built-in MOS input pull-up Pins Section 10A I/O Ports (H8S/2633, H8S/2632, H8S/2631, H8S/2633R) Mode 4 Mode 5 Mode 6 PE7/D7 In 8-bit-bus mode: I/O port PE6/D6 In 16-bit-bus mode: data bus input/output Mode 7 I/O port PE5/D5 PE4/D4 PE3/D3 PE2/D2 PE1/D1 PE0 /D0 Port F • 8-bit I/O port PF7/φ When DDR = 0: input port When DDR = 1 (after reset): φ output When DDR = 0 (after reset): in
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 10A I/O Ports (H8S/2633, H8S/2632, H8S/2631, H8S/2633R) Port Description Port G • 5-bit I/O port Pins Mode 4 Mode 5 Mode 6 Mode 7 PG4 /CS0 When DDR = 0* : input port When DDR = 1*2: CS0 output I/O port PG3 /CS1 When DDR = 0 (after reset): input port PG2 /CS2 When DDR = 1: CS1, CS2, CS3 outputs I/O port, IRQ7 input 1 PG1 /CS3/ OE/IRQ7 OE output, IRQ7 input PG0 /CAS/ IRQ6 DRAM space set: CAS output Otherwise (after
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 10A I/O Ports (H8S/2633, H8S/2632, H8S/2631, H8S/2633R) 10A.2 Port 1 10A.2.1 Overview Port 1 is an 8-bit I/O port.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 10A I/O Ports (H8S/2633, H8S/2632, H8S/2631, H8S/2633R) 10A.2.2 Register Configuration Table 10A.2 shows the port 1 register configuration. Table 10A.2 Port 1 Registers Address* Name Abbreviation R/W Initial Value Port 1 data direction register P1DDR W H'00 H'FE30 Port 1 data register P1DR R/W H'00 H'FF00 Port 1 register PORT1 R Undefined H'FFB0 Note: * Lower 16 bits of the address.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 10A I/O Ports (H8S/2633, H8S/2632, H8S/2631, H8S/2633R) Port 1 Register (PORT1) Bit : Initial value : R/W : 7 6 5 4 3 2 1 0 P17 —* P16 —* P15 —* P14 —* P13 —* P12 —* P11 —* P10 —* R R R R R R R R Note: * Determined by state of pins P17 to P10. PORT1 is an 8-bit read-only register that shows the pin states. It cannot be written to.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 10A I/O Ports (H8S/2633, H8S/2632, H8S/2631, H8S/2633R) Table 10A.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 10A I/O Ports (H8S/2633, H8S/2632, H8S/2631, H8S/2633R) Pin Selection Method and Pin Functions P16/PO14/ TIOCA2/PWM2/ IRQ1 The pin function is switched as shown below according to the combination of the TPU channel 2 setting (by bits MD3 to MD0 in TMDR2, bits IOA3 to IOA0 in TIOR2, and bits CCLR1 and CCLR0 in TCR2), OEA bit in DACR3, bit NDER14 in NDERH, and bit P16DDR.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 10A I/O Ports (H8S/2633, H8S/2632, H8S/2631, H8S/2633R) Pin Selection Method and Pin Functions P15/PO13/ TIOCB1/TCLKC The pin function is switched as shown below according to the combination of the TPU channel 1 setting (by bits MD3 to MD0 in TMDR1, bits IOB3 to IOB0 in TIOR1, and bits CCLR1 and CCLR0 in TCR1), bits TPSC2 to TPSC0 in TCR0, TCR2, TCR4, and TCR5, bit NDER13 in NDERH, and bit P15DDR.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 10A I/O Ports (H8S/2633, H8S/2632, H8S/2631, H8S/2633R) Pin Selection Method and Pin Functions P14/PO12/ TIOCA1/IRQ0 The pin function is switched as shown below according to the combination of the TPU channel 1 setting (by bits MD3 to MD0 in TMDR1, bits IOA3 to IOA0 in TIOR1, and bits CCLR1 and CCLR0 in TCR1), bit NDER12 in NDERH, and bit P14DDR.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 10A I/O Ports (H8S/2633, H8S/2632, H8S/2631, H8S/2633R) Pin Selection Method and Pin Functions P13/PO11/ TIOCD0/TCLKB/ A23 The pin function is switched as shown below according to the combination of the operating mode, and the TPU channel 0 setting (by bits MD3 to MD0 in TMDR0, bits IOD3 to IOD0 in TIOR0L, and bits CCLR2 to CCLR0 in TCR0), bits TPSC2 to TPSC0 in TCR0 to TCR2, bits AE3 to AE0 in PFCR, bit NDER11 in NDERH, and bit
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Pin P13/PO11/ TIOCD0/TCLKB/ A23 (cont) Section 10A I/O Ports (H8S/2633, H8S/2632, H8S/2631, H8S/2633R) Selection Method and Pin Functions TPU Channel 0 Setting (2) MD3 to MD0 IOD3 to IOD0 (1) B'0000 B'0000 (2) (2) B'0010 B'0100 B'0001 to B'0011 B'1xxx B'0101 to (1) (2) B'0011 — B'xx00 Other than B'xx00 B'0111 CCLR2 to CCLR0 — — — — Other than B'110 B'110 Output function — Output compare output — — PWM mode
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 10A I/O Ports (H8S/2633, H8S/2632, H8S/2631, H8S/2633R) Pin Selection Method and Pin Functions P12/PO10/ TIOCC0/TCLKA/ A22 The pin function is switched as shown below according to the combination of the operating mode, and the TPU channel 0 setting (by bits MD3 to MD0 in TMDR0, bits IOC3 to IOC0 in TIOR0L, and bits CCLR2 to CCLR0 in TCR0), bits TPSC2 to TPSC0 in TCR0 to TCR5, bits AE3 to AE0 in PFCR, bit NDER10 in NDERH, and bit
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Pin P12/PO10/ TIOCC0/TCLKA/ A22 (cont) Section 10A I/O Ports (H8S/2633, H8S/2632, H8S/2631, H8S/2633R) Selection Method and Pin Functions TPU Channel 0 Setting (2) MD3 to MD0 IOC3 to IOC0 (1) B'0000 B'0000 B'0100 B'0001 to B'0011 B'1xxx B'0101 to (2) (1) B'001x B'0010 B'xx00 (1) (2) B'0011 Other than B'xx00 B'0111 CCLR2 to CCLR0 — — — — Other than B'101 B'101 Output function — Output compare output — PWM mode
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 10A I/O Ports (H8S/2633, H8S/2632, H8S/2631, H8S/2633R) Pin Selection Method and Pin Functions P11/PO9/TIOCB0/ The pin function is switched as shown below according to the combination of DACK1/A21 the operating mode, and the TPU channel 0 setting (by bits MD3 to MD0 in TMDR0, and bits IOB3 to IOB0 in TIOR0H), bits AE3 to AE0 in PFCR, bit NDER9 in NDERH, SAE1 bit in DMABCRH, and bit P11DDR.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Pin Section 10A I/O Ports (H8S/2633, H8S/2632, H8S/2631, H8S/2633R) Selection Method and Pin Functions P11/PO9/TIOCB0/ TPU Channel DACK1/A21 (cont) 0 Setting (2) MD3 to MD0 IOB3 to IOB0 (1) B'0000 B'0000 (2) (2) B'0010 B'0100 B'0001 to B'0011 B'1xxx B'0101 to (1) (2) B'0011 — B'xx00 Other than B'xx00 B'0111 CCLR2 to CCLR0 — — — — Other than B'010 B'010 Output function — Output compare output — — PWM mode 2
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 10A I/O Ports (H8S/2633, H8S/2632, H8S/2631, H8S/2633R) Pin Selection Method and Pin Functions P10/PO8/TIOCA0/ The pin function is switched as shown below according to the combination of DACK0/A20 the operating mode, and the TPU channel 0 setting (by bits MD3 to MD0 in TMDR0, bits IOA3 to IOA0 in TIOR0H, and bits CCLR2 to CCLR0 in TCR0), bits AE3 to AE0 in PFCR, bit NDER8 in NDERH, SAE0 bit in DMABCRH, and bit P10DDR.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Pin P10/PO8/TIOCA0/ DACK0/A20 (cont) Section 10A I/O Ports (H8S/2633, H8S/2632, H8S/2631, H8S/2633R) Selection Method and Pin Functions TPU Channel 0 Setting (2) MD3 to MD0 IOA3 to IOA0 (1) B'0000 B'0000 B'0100 B'0001 to B'0011 B'1xxx B'0101 to (2) (1) B'001x B'0010 B'xx00 (1) (2) B'0011 Other than B'xx00 B'0111 CCLR2 to CCLR0 — — — — Other than B'001 B'001 Output function — Output compare output — PWM mode 1
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 10A I/O Ports (H8S/2633, H8S/2632, H8S/2631, H8S/2633R) 10A.3 Port 3 10A.3.1 Overview Port 3 is an 8-bit I/O port. Port 3 is a multi-purpose port for SCI I/O pins (TxD0, RxD0, SCK0, IrTxD, IrRxD, TxD1, RxD1, SCK1, TxD4, RxD4, and SCK4), external interrupt input pins (IRQ4 and IRQ5) and IIC I/O pins (SCL0, SDA0, SCL1, and SDA1). All of the port 3 pin functions have the same operating mode.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 10A I/O Ports (H8S/2633, H8S/2632, H8S/2631, H8S/2633R) Port 3 Data Direction Register (P3DDR) Bit 7 : 6 5 4 3 2 1 0 P37DDR P36DDR P35DDR P34DDR P33DDR P32DDR P31DDR P30DDR Initial value : 0 0 0 0 0 0 0 0 R/W W W W W W W W W : P3DDR is an 8-bit write-dedicated register, which specifies the I/O for each port 3 pin by bit. Read is disenabled. If a read is carried out, undefined values are read out.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 10A I/O Ports (H8S/2633, H8S/2632, H8S/2631, H8S/2633R) PORT3 is an 8-bit read-dedicated register, which reflects the state of pins. Write is disenabled. Always carry out writing off output data of port 3 pins (P37 to P30) to P3DR without fail. When P3DDR is set to 1, if PORT3 is read, the values of P3DR are read. When P3DDR is cleared to 0, if PORT3 is read, the states of pins are read out.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 10A I/O Ports (H8S/2633, H8S/2632, H8S/2631, H8S/2633R) Table 10A.5 Port 3 Pin Functions Pin Selection Method and Pin Functions P37/TxD4 Switches as follows according to combinations of SCR TE bit of SCI4 and the P37DDR bit. TE 0 P37DDR Pin function 1 0 1 — P37 input pin P37 output pin* TxD4 output pin Note: * When P37ODR = 1, it becomes NMOS open drain output.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 10A I/O Ports (H8S/2633, H8S/2632, H8S/2631, H8S/2633R) Pin Selection Method and Pin Functions P34/RxD1/ SDA0 Switches as follows according to combinations of ICCR0 ICE bit of IIC0, SCR RE bit of SCI1, and the P34DDR bit. The SDA0 output format becomes NMOS open drain output, enabling direct bus driving.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 10A I/O Ports (H8S/2633, H8S/2632, H8S/2631, H8S/2633R) Pin Selection Method and Pin Functions P31/RxD0/ IrRxD Switches as follows according to combinations of SCR RE bit of SCI0 and the P31DDR bit. RE P31DDR Pin function 0 1 0 1 — P31 input pin P31 output pin* RxD0/IrRxD input pin Note: * When P31ODR = 1, it becomes NMOS open drain output.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 10A I/O Ports (H8S/2633, H8S/2632, H8S/2631, H8S/2633R) 10A.4 Port 4 10A.4.1 Overview Port 4 is an 8-bit input-only port. Port 4 pins also function as A/D converter analog input pins (AN0 to AN7) and D/A converter analog output pins (DA0 and DA1). Port 4 pin functions are the same in all operating modes. Figure 10A.3 shows the port 4 pin configuration.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 10A I/O Ports (H8S/2633, H8S/2632, H8S/2631, H8S/2633R) 10A.4.2 Register Configuration Table 10A.6 shows the port 4 register configuration. Port 4 is an input-only port, and does not have a data direction register or data register. Table 10A.6 Port 4 Registers Name Abbreviation R/W Initial Value Address* Port 4 register PORT4 R Undefined H'FFB3 Note: * Lower 16 bits of the address.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 10A I/O Ports (H8S/2633, H8S/2632, H8S/2631, H8S/2633R) 10A.5 Port 7 10A.5.1 Overview Port 7 is an 8-bit I/O port. Port 7 is a multipurpose port for the 8-bit timer I/O pins (TMRI01, TMCI01, TMRI23, TMCI23, TMO0, TMO1, TMO2, and TMO3), DMAC I/O pins (DREQ0, TEND0, DREQ1, and TEND1), bus control output pins (CS4 to CS7), SCI I/O pins (SCK3, RxD3, and TxD3) and manual reset input pin (MRES).
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 10A I/O Ports (H8S/2633, H8S/2632, H8S/2631, H8S/2633R) 10A.5.2 Register Configuration Table 10A.7 shows the port 7 register configuration. Table 10A.7 Port 7 Register Configuration Name Abbreviation R/W Initial Value Address* Port 7 data direction register P7DDR W H'00 H'FE36 Port 7 data register P7DR R/W H'00 H'FF06 Port 7 register PORT7 R Undefined H'FFB6 Note: * Lower 16 bits of the address.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 10A I/O Ports (H8S/2633, H8S/2632, H8S/2631, H8S/2633R) Port 7 Data Register (P7DR) Bit : Initial value : R/W : 7 6 5 4 3 2 1 0 P77DR P76DR P75DR P74DR P73DR P72DR P71DR P70DR 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W P7DR is an 8-bit readable/writable register, which stores the output data of port 7 pins (P77 to P70).
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 10A I/O Ports (H8S/2633, H8S/2632, H8S/2631, H8S/2633R) 10A.5.3 Pin Functions The pins of port 7 are multipurpose pins which function as 8-bit timer I/O pins, (TMRI01, TMCI01, TMRI23, TMCI23, TMO0, TMO1, TMO2, and TMO3), DMAC I/O pins (DREQ0, TEND0, DREQ1, and TEND1), bus control output pins (CS4 to CS7), SCI I/O pins (SCK3, RxD3, and TxD3) and manual reset input pin (MRES). Table 10A.8 shows the functions of port 7 pins.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 10A I/O Ports (H8S/2633, H8S/2632, H8S/2631, H8S/2633R) Pin Selection Method and Pin Functions P74/TMO2/ MRES Switches as follows according to combinations of TCSR2 OS3 to OS0 bits of the 8bit timer, SYSCR MRESE bit and the P74DDR bit.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Pin Section 10A I/O Ports (H8S/2633, H8S/2632, H8S/2631, H8S/2633R) Selection Method and Pin Functions P71/TMRI23/ Switches as follows according to operating mode and P71DDR.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 10A I/O Ports (H8S/2633, H8S/2632, H8S/2631, H8S/2633R) 10A.6 Port 9 10A.6.1 Overview Port 9 is an 8-bit input-only port. Port 9 pins also function as A/D converter analog input pins (AN8 to AN15) and D/A converter analog output pins (DA2 and DA3). Port 9 pin functions are the same in all operating modes. Figure 10A.5 shows the port 9 pin configuration.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 10A I/O Ports (H8S/2633, H8S/2632, H8S/2631, H8S/2633R) 10A.6.2 Register Configuration Table 10A.9 shows the port 9 register configuration. Port 9 is an input-only port, and does not have a data direction register or data register. Table 10A.9 Port 9 Registers Name Abbreviation R/W Initial Value Address* Port 9 register PORT9 R Undefined H'FFB8 Note: * Lower 16 bits of the address.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 10A I/O Ports (H8S/2633, H8S/2632, H8S/2631, H8S/2633R) 10A.7 Port A 10A.7.1 Overview Port A is a 4-bit I/O port. Port A pins also function as SCI2 I/O pins (SCK2, RxD2, and TxD2) and as address bus outputs. The pin functions change according to the operating mode. Port A has a built-in MOS input pull-up function that can be controlled by software. Figure 10A.6 shows the port A pin configuration.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 10A I/O Ports (H8S/2633, H8S/2632, H8S/2631, H8S/2633R) 10A.7.2 Register Configuration Table 10A.10 shows the port A register configuration. Table 10A.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 10A I/O Ports (H8S/2633, H8S/2632, H8S/2631, H8S/2633R) • Mode 7 Setting a PADDR bit to 1 makes the corresponding port A pin an output port, while clearing the bit to 0 makes the pin an input port.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 10A I/O Ports (H8S/2633, H8S/2632, H8S/2631, H8S/2633R) Port A MOS Pull-Up Control Register (PAPCR) Bit : 7 6 5 4 — — — — Initial value : Undefined Undefined Undefined Undefined R/W : — — — — 3 2 1 0 PA3PCR PA2PCR PA1PCR PA0PCR 0 0 0 0 R/W R/W R/W R/W PAPCR is an 8-bit readable/writable register that controls the MOS input pull-up function incorporated into port A on an individual bit basis.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 10A I/O Ports (H8S/2633, H8S/2632, H8S/2631, H8S/2633R) 10A.7.3 Pin Functions Port A pins also function as SCI input/output pins (TxD2, RxD2, SCK2) and address bus output pins (A19 to A16). Port A pin functions are shown in table 10A.11. Table 10A.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 10A I/O Ports (H8S/2633, H8S/2632, H8S/2631, H8S/2633R) Pin Selection Method and Pin Functions PA2/A18/RxD2 The pin function is switched as shown below according to the operating mode, bits AE3 to AE0 in PFCR, bit RE in SCR of SCI2, and bit PA2DDR.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 10A I/O Ports (H8S/2633, H8S/2632, H8S/2631, H8S/2633R) Pin Selection Method and Pin Functions PA0/A16 The pin function is switched as shown below according to the operating mode, bits AE3 to AE0 in PFCR, and bit PA0DDR.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 10A I/O Ports (H8S/2633, H8S/2632, H8S/2631, H8S/2633R) 10A.7.4 MOS Input Pull-Up Function Port A has a built-in MOS input pull-up function that can be controlled by software. MOS input pull-up can be specified as on or off on an individual bit basis.
Section 10A I/O Ports (H8S/2633, H8S/2632, H8S/2631, H8S/2633R) H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 10A.8 Port B 10A.8.1 Overview Port B is an 8-bit I/O port. Port B pins also function as TPU I/O pins (TIOCA3, TIOCB3, TIOCC3, TIOCD3, TIOCA4, TIOCB4, TIOCA5, and TIOCB5) and as address outputs; the pin functions change according to the operating mode. Port B has a built-in MOS input pull-up function that can be controlled by software. Figure 10A.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 10A I/O Ports (H8S/2633, H8S/2632, H8S/2631, H8S/2633R) 10A.8.2 Register Configuration Table 10A.13 shows the port B register configuration. Table 10A.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 10A I/O Ports (H8S/2633, H8S/2632, H8S/2631, H8S/2633R) Port B Data Register (PBDR) Bit : Initial value : R/W : 7 6 5 4 3 2 1 0 PB7DR PB6DR PB5DR PB4DR PB3DR PB2DR PB1DR PB0DR 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W PBDR is an 8-bit readable/writable register that stores output data for the port B pins (PB7 to PB0).
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 10A I/O Ports (H8S/2633, H8S/2632, H8S/2631, H8S/2633R) Port B MOS Pull-Up Control Register (PBPCR) Bit : 7 6 5 4 3 2 1 0 PB7PCR PB6PCR PB5PCR PB4PCR PB3PCR PB2PCR PB1PCR PB0PCR Initial value : R/W : 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W PBPCR is an 8-bit readable/writable register that controls the MOS input pull-up function incorporated into port B on an individual bit basis.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 10A I/O Ports (H8S/2633, H8S/2632, H8S/2631, H8S/2633R) 10A.8.3 Pin Functions Port B pins also function as TPU output pins (TIOCA3, TIOCB3, TIOCC3, TIOCD3, TIOCA4, TIOCB4, TIOCC4, and TIOCD4) and address bus output pins (A15 to A8). Table 10A.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Pin PB7/A15/TIOCB5 Section 10A I/O Ports (H8S/2633, H8S/2632, H8S/2631, H8S/2633R) Selection Method and Pin Functions TPU Channel 5 Setting (2) MD3 to MD0 B'0000, B'01xx IOB3 to IOB0 B'0000 B'0100 B'1xxx (1) B'0001 to B'0011 (2) (2) B'0010 (1) (2) B'0011 — B'xx00 Other than B'xx00 B'0101 to B'0111 CCLR1, CCLR0 — — — — Other than B'10 B'10 Output function — Output compare output — — PWM mode 2 output — x:
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 10A I/O Ports (H8S/2633, H8S/2632, H8S/2631, H8S/2633R) Pin Selection Method and Pin Functions PB6/A14/TIOCA5 The function of this pin changes according to the operating mode and the setting of bits AE3 to AE0 in PFCR; the TPU5 settings of bits MD3 to MD0 in TMDR5, bits IOA3 to IOA0 in TIOR5, and the CCLR1 and CCLR0 bits in TCR5; and the setting of the PB6DDR bit.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Pin Section 10A I/O Ports (H8S/2633, H8S/2632, H8S/2631, H8S/2633R) Selection Method and Pin Functions PB5/A13/TIOCB4 The function of this pin changes according to the operating mode and the setting of bits AE3 to AE0 in PFCR; the TPU4 settings of bits MD3 to MD0 in TMDR4, bits IOB3 to IOB0 in TIOR4, and the CCLR1 and CCLR0 bits in TCR4; and the setting of the PB5DDR bit.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 10A I/O Ports (H8S/2633, H8S/2632, H8S/2631, H8S/2633R) Pin Selection Method and Pin Functions PB4/A12/TIOCA4 The function of this pin changes according to the operating mode and the setting of bits AE3 to AE0 in PFCR; the TPU4 settings of bits MD3 to MD0 in TMDR4, bits IOA3 to IOA0 in TIOR4, and the CCLR1 and CCLR0 bits in TCR4; and the setting of the PB4DDR bit.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Pin Section 10A I/O Ports (H8S/2633, H8S/2632, H8S/2631, H8S/2633R) Selection Method and Pin Functions PB3/A11/TIOCD3 The function of this pin changes according to the operating mode and the setting of bits AE3 to AE0 in PFCR; the TPU3 settings of bits MD3 to MD0 in TMDR3, bits IOD3 to IOD0 in TIORL3, and bits CCLR2 to CCLR0 in TCR3; and the setting of the PB3DDR bit.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 10A I/O Ports (H8S/2633, H8S/2632, H8S/2631, H8S/2633R) Pin Selection Method and Pin Functions PB2/A10/TIOCC3 The function of this pin changes according to the operating mode and the setting of bits AE3 to AE0 in PFCR; the TPU3 settings of bits MD3 to MD0 in TMDR3, bits IOC3 to IOC0 in TIORL3, and bits CCLR2 to CCLR0 in TCR3; and the setting of the PB2DDR bit.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 10A I/O Ports (H8S/2633, H8S/2632, H8S/2631, H8S/2633R) Pin Selection Method and Pin Functions PB1/A9/TIOCB3 The function of this pin changes according to the operating mode and the setting of bits AE3 to AE0 in PFCR; the TPU3 settings of bits MD3 to MD0 in TMDR3, bits IOB3 to IOB0 in TIORH3, and bits CCLR2 to CCLR0 in TCR3; and the setting of the PB1DDR bit.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 10A I/O Ports (H8S/2633, H8S/2632, H8S/2631, H8S/2633R) Pin Selection Method and Pin Functions PB0/A8/TIOCA3 The function of this pin changes according to the operating mode and the setting of bits AE3 to AE0 in PFCR; the TPU3 settings of bits MD3 to MD0 in TMDR3, bits IOA3 to IOA0 in TIORH3, and bits CCLR2 to CCLR0 in TCR3; and the setting of the PB0DDR bit.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 10A I/O Ports (H8S/2633, H8S/2632, H8S/2631, H8S/2633R) 10A.8.4 MOS Input Pull-Up Function Port B has a built-in MOS input pull-up function that can be controlled by software. MOS input pull-up can be specified as on or off on an individual bit basis.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 10A I/O Ports (H8S/2633, H8S/2632, H8S/2631, H8S/2633R) 10A.9 Port C 10A.9.1 Overview Port C is an 8-bit I/O port. Port C pins also function as a 14-bit PWM output (PWM0 and PWM1) and as an address bus outputs. The pin functions change according to the operating mode. Port C has a built-in MOS input pull-up function that can be controlled by software. Figure 10A.8 shows the port C pin configuration.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 10A I/O Ports (H8S/2633, H8S/2632, H8S/2631, H8S/2633R) 10A.9.2 Register Configuration Table 10A.16 shows the port C register configuration. Table 10A.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 10A I/O Ports (H8S/2633, H8S/2632, H8S/2631, H8S/2633R) Port C Data Register (PCDR) Bit : Initial value : R/W : 7 6 5 4 3 2 1 0 PC7DR PC6DR PC5DR PC4DR PC3DR PC2DR PC1DR PC0DR 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W PCDR is an 8-bit readable/writable register that stores output data for the port C pins (PC7 to PC0).
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 10A I/O Ports (H8S/2633, H8S/2632, H8S/2631, H8S/2633R) Port C MOS Pull-Up Control Register (PCPCR) Bit : 7 6 5 4 3 2 1 0 PC7PCR PC6PCR PC5PCR PC4PCR PC3PCR PC2PCR PC1PCR PC0PCR Initial value : R/W : 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W PCPCR is an 8-bit readable/writable register that controls the MOS input pull-up function incorporated into port C on an individual bit basis.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 10A I/O Ports (H8S/2633, H8S/2632, H8S/2631, H8S/2633R) 10A.9.3 Pin Functions for Each Mode (1) Modes 4 and 5 In modes 4 and 5, port C pins function as address outputs automatically. Figure 10A.9 shows the port C pin functions. A7 (output) A6 (output) A5 (output) Port C A4 (output) A3 (output) A2 (output) A1 (output) A0 (output) Figure 10A.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Port C Section 10A I/O Ports (H8S/2633, H8S/2632, H8S/2631, H8S/2633R) PCDDR= 1 PCDDR= 0 A7 (output) PC7 (input) / PWM1 (output) A6 (output) PC6 (input) / PWM0 (output) A5 (output) PC5 (input) A4 (output) PC4 (input) A3 (output) PC3 (input) A2 (output) PC2 (input) A1 (output) PC1 (input) A0 (output) PC0 (input) Figure 10A.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 10A I/O Ports (H8S/2633, H8S/2632, H8S/2631, H8S/2633R) 10A.9.4 MOS Input Pull-Up Function Port C has a built-in MOS input pull-up function that can be controlled by software. This MOS input pull-up function can be used in modes 6 and 7, and can be specified as on or off on an individual bit basis. In modes 6 and 7, when PCPCR is set to 1 in the input state by setting of DACR and PCDDR, the MOS input pull-up is set to ON.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 10A I/O Ports (H8S/2633, H8S/2632, H8S/2631, H8S/2633R) 10A.10 Port D 10A.10.1 Overview Port D is an 8-bit I/O port. Port D has a data bus I/O function, and the pin functions change according to the operating mode. Port D has a built-in MOS input pull-up function that can be controlled by software. Figure 10A.12 shows the port D pin configuration.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 10A I/O Ports (H8S/2633, H8S/2632, H8S/2631, H8S/2633R) 10A.10.2 Register Configuration Table 10A.18 shows the port D register configuration. Table 10A.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 10A I/O Ports (H8S/2633, H8S/2632, H8S/2631, H8S/2633R) Port D Data Register (PDDR) Bit : Initial value : R/W : 7 6 5 4 3 2 1 0 PD7DR PD6DR PD5DR PD4DR PD3DR PD2DR PD1DR PD0DR 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W PDDR is an 8-bit readable/writable register that stores output data for the port D pins (PD7 to PD0).
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 10A I/O Ports (H8S/2633, H8S/2632, H8S/2631, H8S/2633R) Port D MOS Pull-Up Control Register (PDPCR) Bit : 7 6 5 4 3 2 1 0 PD7PCR PD6PCR PD5PCR PD4PCR PD3PCR PD2PCR PD1PCR PD0PCR Initial value : R/W : 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W PDPCR is an 8-bit readable/writable register that controls the MOS input pull-up function incorporated into port D on an individual bit basis.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 10A I/O Ports (H8S/2633, H8S/2632, H8S/2631, H8S/2633R) Port D pin functions in mode 7 are shown in figure 10A.14. PD7 (I/O) PD6 (I/O) PD5 (I/O) Port D PD4 (I/O) PD3 (I/O) PD2 (I/O) PD1 (I/O) PD0 (I/O) Figure 10A.14 Port D Pin Functions (Mode 7) 10A.10.4 MOS Input Pull-Up Function Port D has a built-in MOS input pull-up function that can be controlled by software.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 10A I/O Ports (H8S/2633, H8S/2632, H8S/2631, H8S/2633R) 10A.11 Port E 10A.11.1 Overview Port E is an 8-bit I/O port. Port E has a data bus I/O function, and the pin functions change according to the operating mode and whether 8-bit or 16-bit bus mode is selected. Port E has a built-in MOS input pull-up function that can be controlled by software. Figure 10A.15 shows the port E pin configuration.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 10A I/O Ports (H8S/2633, H8S/2632, H8S/2631, H8S/2633R) 10A.11.2 Register Configuration Table 10A.20 shows the port E register configuration. Table 10A.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 10A I/O Ports (H8S/2633, H8S/2632, H8S/2631, H8S/2633R) Port E Data Register (PEDR) Bit : Initial value : R/W : 7 6 5 4 3 2 1 0 PE7DR PE6DR PE5DR PE4DR PE3DR PE2DR PE1DR PE0DR 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W PEDR is an 8-bit readable/writable register that stores output data for the port E pins (PE7 to PE0).
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 10A I/O Ports (H8S/2633, H8S/2632, H8S/2631, H8S/2633R) PEPCR is an 8-bit readable/writable register that controls the MOS input pull-up function incorporated into port E on an individual bit basis. When a PEDDR bit is cleared to 0 (input port setting) with 8-bit bus mode selected in modes 4, 5, or 6, or in mode 7, setting the corresponding PEPCR bit to 1 turns on the MOS input pull-up for the corresponding pin.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 10A I/O Ports (H8S/2633, H8S/2632, H8S/2631, H8S/2633R) PE7 (I/O) PE6 (I/O) PE5 (I/O) Port E PE4 (I/O) PE3 (I/O) PE2 (I/O) PE1 (I/O) PE0 (I/O) Figure 10A.17 Port E Pin Functions (Mode 7) 10A.11.4 MOS Input Pull-Up Function Port E has a built-in MOS input pull-up function that can be controlled by software.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 10A I/O Ports (H8S/2633, H8S/2632, H8S/2631, H8S/2633R) 10A.12 Port F 10A.12.1 Overview Port F is an 8-bit I/O port. Port F pins also function as external interrupt input pins (IRQ2 and IRQ3), BUZZ output pin, A/D trigger input pin (ADTRG), bus control signal input/output pins (AS, RD, HWR, LWR, LCAS, WAIT, BREQO, BREQ, and BACK) and the system clock (φ) output pin. Figure 10A.18 shows the port F pin configuration.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 10A I/O Ports (H8S/2633, H8S/2632, H8S/2631, H8S/2633R) 10A.12.2 Register Configuration Table 10A.22 shows the port F register configuration. Table 10A.22 Port F Registers Name Abbreviation R/W Initial Value 1 Address* Port F data direction register PFDDR W 2 H'80/H'00* H'FE3E Port F data register PFDR R/W H'00 H'FF0E Port F register PORTF R Undefined H'FFBE Notes: 1. Lower 16 bits of the address. 2.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 10A I/O Ports (H8S/2633, H8S/2632, H8S/2631, H8S/2633R) Pins PF2 to PF0 are designated as bus control input/output pins (LCAS, WAIT, BREQO, BACK, and BREQ) by means of bus controller settings. At other times, setting a PFDDR bit to 1 makes the corresponding port F pin an output port, while clearing the bit to 0 makes the pin an input port.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 10A I/O Ports (H8S/2633, H8S/2632, H8S/2631, H8S/2633R) 10A.12.3 Pin Functions Port F pins also function as external interrupt input pins (IRQ2 and IRQ3), BUZZ output pin, A/D trigger input pin (ADTRG), bus control signal input/output pins (AS, RD, HWR, LWR, LCAS, WAIT, BREQO, BREQ, and BACK) and the system clock (φ) output pin. The pin functions differ between modes 4 to 6, and mode 7. Port F pin functions are shown in table 10A.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 10A I/O Ports (H8S/2633, H8S/2632, H8S/2631, H8S/2633R) Pin Selection Method and Pin Functions PF4/HWR The pin function is switched as shown below according to the operating mode and bit PF4DDR.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 10A I/O Ports (H8S/2633, H8S/2632, H8S/2631, H8S/2633R) Pin Selection Method and Pin Functions PF1/BACK/ BUZZ The pin function is switched as shown below according to the combination of the operating mode and bits BRLE, BUZZE, and PF1DDR.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 10A I/O Ports (H8S/2633, H8S/2632, H8S/2631, H8S/2633R) 10A.13 Port G 10A.13.1 Overview Port G is a 5-bit I/O port and also used as external interrupt input pins (IRQ6 and IRQ7) and bus control signal output pins (CS0 to CS3, CAS, and OE). Figure 10A.19 shows the configuration of port G pins.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 10A I/O Ports (H8S/2633, H8S/2632, H8S/2631, H8S/2633R) 10A.13.2 Register Configuration Table 10A.24 shows the port G register configuration. Table 10A.24 Port G Registers Name Abbreviation R/W 2 1 Initial Value* Address* Port G data direction register PGDDR W 3 H'10/H'00* H'FE3F Port G data register PGDR R/W H'00 H'FF0F Port G register PORTG R Undefined H'FFBF Notes: 1. Lower 16 bits of the address. 2.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 10A I/O Ports (H8S/2633, H8S/2632, H8S/2631, H8S/2633R) When the DRAM interface is set, pin PG0 functions as the CAS output pin. When PGDDR is set to 1, the pin functions as an output port. When PGDDR is cleared to 0, the pin functions as an input port. See section 7, Bus Controller, for the DRAM interface. • Mode 7 PGDDR to 1 it becomes an output port, and by clearing it to 0 it becomes an input port.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 10A I/O Ports (H8S/2633, H8S/2632, H8S/2631, H8S/2633R) In power-on reset or hardware standby mode, port G is determined by the pin state because PGDDR and PGDR are initialized. In manual reset or software standby mode, the last state is retained. 10A.13.3 Pin Functions Port G is used also as external interrupt input pins (IRQ6 and IRQ7) and bus control signal output pins (CS0 to CS3, CAS, and OE).
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 10A I/O Ports (H8S/2633, H8S/2632, H8S/2631, H8S/2633R) Pin Selection Method and Pin Functions PG1/CS3/ OE/IRQ7 The pin function is switched as shown below according to the operating mode and bits OES and PG1DDR in BCRL.
Section 10A I/O Ports (H8S/2633, H8S/2632, H8S/2631, H8S/2633R) Page 458 of 1434 H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 R01UH0166EJ0600 Rev. 6.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 10B I/O Ports (H8S/2695) Section 10B I/O Ports (H8S/2695) 10B.1 Overview The H8S/2633 Group has 10 I/O ports (ports 1, 3, 7 and A to G), and two input-only port (ports 4 and 9). Table 10B.1 summarizes the port functions. The pins of each port also have other functions.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 10B I/O Ports (H8S/2695) Table 10B.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Port Description Port 7 8-bit I/O port Pins P77/TxD3 P76/RxD3 P75/SCK3 Section 10B I/O Ports (H8S/2695) Mode 4 Mode 5 Mode 6 8-bit I/O port also functioning as bus control output pins (CS4 to CS7), SCI I/O pins (SCK3, RxD3, TxD3), and the manual reset input pin (MRES) P74/MRES P73/CS7 P72/CS6 P71/CS5 Mode 7 8-bit I/O port also functioning as SCI I/O pins (SCK3, RxD3, TxD3) and the manual reset input pin (MRES) P70/CS4 Port 9 •
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 10B I/O Ports (H8S/2695) Port Description Pins Mode 4 Mode 5 Mode 6 Mode 7 8-bit I/O port also functioning as address outputs (A7 to A0) 8-bit I/O port also functioning Data bus input/output I/O port PE7/D7 In 8-bit-bus mode: I/O port I/O port PE6/D6 In 16-bit-bus mode: data bus input/output Port C 8-bit I/O port PC7/A7 Built-in MOS input pull-up PC6/A6 Open-drain output capability PC4/A4 PC5/A5 PC3/A3 PC2/A2 P
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Port Description Port F • 8-bit I/O port Pins PF7/φ Section 10B I/O Ports (H8S/2695) Mode 4 Mode 5 Mode 6 When DDR = 0: input port When DDR = 1 (after reset): φ output Mode 7 When DDR = 0 (after reset): input port When DDR = 1: φ output PF6/AS RD, HWR, LWR outputs I/O port PF5/RD ADTRG, IRQ3 input ADTRG, IRQ3 input When WAITE = 0 and BREQOE = 0 (after reset): I/O port I/O port PF4/HWR PF3/LWR/ADTRG/ IRQ3 PF2/WAIT/BREQO
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 10B I/O Ports (H8S/2695) 10B.2 Port 1 10B.2.1 Overview Port 1 is an 8-bit I/O port. Port 1 pins also function as TPU I/O pins (TCLKA, TCLKB, TCLKC, TCLKD, TIOCA0, TIOCB0, TIOCC0, TIOCD0, TIOCA1, TIOCB1, TIOCA2, and TIOCB2), external interrupt pins (IRQ0 and IRQ1), and address bus output pins (A23 to A20). Port 1 pin functions change according to the operating mode. Figure 10B.1 shows the port 1 pin configuration.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 10B I/O Ports (H8S/2695) 10B.2.2 Register Configuration Table 10B.2 shows the port 1 register configuration. Table 10B.2 Port 1 Registers Address* Name Abbreviation R/W Initial Value Port 1 data direction register P1DDR W H'00 H'FE30 Port 1 data register P1DR R/W H'00 H'FF00 Port 1 register PORT1 R Undefined H'FFB0 Note: * Lower 16 bits of the address.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 10B I/O Ports (H8S/2695) P1DR is initialized to H'00 by a power-on reset, and in hardware standby mode. It retains its prior state by a manual reset or in software standby mode. Port 1 Register (PORT1) Bit : Initial value : R/W : 7 6 5 4 3 2 1 0 P17 —* P16 —* P15 —* P14 —* P13 —* P12 —* P11 —* P10 —* R R R R R R R R Note: * Determined by state of pins P17 to P10.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 10B I/O Ports (H8S/2695) 10B.2.3 Pin Functions Port 1 pins also function as TPU I/O pins (TCLKA, TCLKB, TCLKC, TCLKD, TIOCA0, TIOCB0, TIOCC0, TIOCD0, TIOCA1, TIOCB1, TIOCA2, and TIOCB2), external interrupt input pins (IRQ0 and IRQ1), and address bus output pins (A23 to A20). Port 1 pin functions are shown in table 10B.3. Table 10B.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 10B I/O Ports (H8S/2695) Pin Selection Method and Pin Functions P16/TIOCA2/ IRQ1 The pin function is switched as shown below according to the combination of the TPU channel 2 setting (by bits MD3 to MD0 in TMDR2, bits IOA3 to IOA0 in TIOR2, and bits CCLR1 and CCLR0 in TCR2), and bit P16DDR.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 10B I/O Ports (H8S/2695) Pin Selection Method and Pin Functions P15/TIOCB1/ TCLKC The pin function is switched as shown below according to the combination of the TPU channel 1 setting (by bits MD3 to MD0 in TMDR1, bits IOB3 to IOB0 in TIOR1, and bits CCLR1 and CCLR0 in TCR1), bits TPSC2 to TPSC0 in TCR0, TCR2, TCR4, and TCR5, and bit P15DDR.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 10B I/O Ports (H8S/2695) Pin Selection Method and Pin Functions P14/TIOCA1/ IRQ0 The pin function is switched as shown below according to the combination of the TPU channel 1 setting (by bits MD3 to MD0 in TMDR1, bits IOA3 to IOA0 in TIOR1, and bits CCLR1 and CCLR0 in TCR1), and bit P14DDR.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 10B I/O Ports (H8S/2695) Pin Selection Method and Pin Functions P13/TIOCD0/ TCLKB/A23 The pin function is switched as shown below according to the combination of the operating mode, and the TPU channel 0 setting (by bits MD3 to MD0 in TMDR0, bits IOD3 to IOD0 in TIOR0L, and bits CCLR2 to CCLR0 in TCR0), bits TPSC2 to TPSC0 in TCR0 to TCR2, bits AE3 to AE0 in PFCR, and bit P13DDR.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 10B I/O Ports (H8S/2695) Pin P13/TIOCD0/ TCLKB/A23 (cont) Selection Method and Pin Functions TPU Channel 0 Setting (2) MD3 to MD0 IOD3 to IOD0 (1) B'0000 B'0000 (2) (2) (1) B'0010 B'0100 B'0001 to B'0011 B'1xxx B'0101 to (2) B'0011 — B'xx00 Other than B'xx00 B'0111 CCLR2 to CCLR0 — — — — Other than B'110 B'110 Output function — Output compare output — — PWM mode 2 output — x: Don't care Page 472 of
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 10B I/O Ports (H8S/2695) Pin Selection Method and Pin Functions P12/TIOCC0/ TCLKA/A22 The pin function is switched as shown below according to the combination of the operating mode, and the TPU channel 0 setting (by bits MD3 to MD0 in TMDR0, bits IOC3 to IOC0 in TIOR0L, and bits CCLR2 to CCLR0 in TCR0), bits TPSC2 to TPSC0 in TCR0 to TCR5, bits AE3 to AE0 in PFCR, and bit P12DDR.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 10B I/O Ports (H8S/2695) Pin P12/TIOCC0/ TCLKA/A22 (cont) Selection Method and Pin Functions TPU Channel 0 Setting (2) MD3 to MD0 IOC3 to IOC0 (1) B'0000 B'0000 B'0100 B'0001 to B'0011 B'1xxx B'0101 to (2) (1) B'001x B'0010 B'xx00 (1) (2) B'0011 Other than B'xx00 B'0111 CCLR2 to CCLR0 — — — — Other than B'101 B'101 Output function — Output compare output — PWM mode 1 3 output* PWM mode 2 output — x:
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 10B I/O Ports (H8S/2695) Pin Selection Method and Pin Functions P11/TIOCB0/A21 The pin function is switched as shown below according to the combination of the operating mode, and the TPU channel 0 setting (by bits MD3 to MD0 in TMDR0, and bits IOB3 to IOB0 in TIOR0H), bits AE3 to AE0 in PFCR, and bit P11DDR.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 10B I/O Ports (H8S/2695) Pin P11/TIOCB0/A21 (cont) Selection Method and Pin Functions TPU Channel 0 Setting (2) MD3 to MD0 IOB3 to IOB0 (1) B'0000 B'0000 (2) (2) (1) B'0010 B'0100 B'0001 to B'0011 B'1xxx B'0101 to (2) B'0011 — B'xx00 Other than B'xx00 B'0111 CCLR2 to CCLR0 — — — — Other than B'010 B'010 Output function — Output compare output — — PWM mode 2 output — x: Don't care Page 476 of 1434 R
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 10B I/O Ports (H8S/2695) Pin Selection Method and Pin Functions P10/TIOCA0/A20 The pin function is switched as shown below according to the combination of the operating mode, and the TPU channel 0 setting (by bits MD3 to MD0 in TMDR0, bits IOA3 to IOA0 in TIOR0H, and bits CCLR2 to CCLR0 in TCR0), bits AE3 to AE0 in PFCR, and bit P10DDR.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 10B I/O Ports (H8S/2695) Pin P10/TIOCA0/A20 (cont) Selection Method and Pin Functions TPU Channel 0 Setting (2) MD3 to MD0 IOA3 to IOA0 (1) B'0000 B'0000 B'0100 B'0001 to B'0011 B'1xxx B'0101 to (2) (1) B'001x B'0010 B'xx00 (1) (2) B'0011 Other than B'xx00 B'0111 CCLR2 to CCLR0 — — — — Other than B'001 B'001 Output function — Output compare output — PWM mode 1 2 output* PWM mode 2 output — x: Don't car
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 10B I/O Ports (H8S/2695) 10B.3 Port 3 10B.3.1 Overview Port 3 is an 8-bit I/O port. Port 3 is a multi-purpose port for SCI I/O pins (TxD0, RxD0, SCK0, TxD1, RxD1, SCK1, TxD4, RxD4, and SCK4) and external interrupt input pins (IRQ4 and IRQ5). All of the port 3 pin functions have the same operating mode. The configuration for each of the port 3 pins is shown in figure 10B.2.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 10B I/O Ports (H8S/2695) Port 3 Data Direction Register (P3DDR) Bit : 7 6 5 4 3 2 1 0 P37DDR P36DDR P35DDR P34DDR P33DDR P32DDR P31DDR P30DDR Initial value : 0 0 0 0 0 0 0 0 R/W W W W W W W W W : P3DDR is an 8-bit write-dedicated register, which specifies the I/O for each port 3 pin by bit. Read is disenabled. If a read is carried out, undefined values are read out.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 10B I/O Ports (H8S/2695) Port 3 Register (PORT3) Bit : Initial value : R/W : 7 6 5 4 3 2 1 0 P37 P36 P35 P34 P33 P32 P31 P30 —* —* —* —* —* —* —* —* R R R R R R R R Note: * Determined by the state of pins P37 to P30. PORT3 is an 8-bit read-dedicated register, which reflects the state of pins. Write is disenabled.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 10B I/O Ports (H8S/2695) 10B.3.3 Pin Functions The port 3 pins double as SCI I/O input pins (TxD0, RxD0, SCK0, TxD1, RxD1, SCK1, TxD4, RxD4, SCK4), external interrupt input pins (IRQ4, IRQ5). The functions of port 3 pins are shown in table 10B.5. Table 10B.5 Port 3 Pin Functions Pin Selection Method and Pin Functions P37/TxD4 Switches as follows according to combinations of SCR TE bit of SCI4 and the P37DDR bit.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 10B I/O Ports (H8S/2695) Pin Selection Method and Pin Functions P34/RxD1 Switches as follows according to combinations of ICCR0 ICE bit of IIC0, SCR RE bit of SCI1, and the P34DDR bit. RE 0 P34DDR Pin function 1 0 1 — P34 input pin P34 output pin* RxD1 input pin Note: * Output type is NMOS push-pull. When P34ODR = 1, it becomes NMOS open drain tray.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 10B I/O Ports (H8S/2695) Pin Selection Method and Pin Functions P31/RxD0 Switches as follows according to combinations of SCR RE bit of SCI0 and the P31DDR bit. RE P31DDR Pin function 0 1 0 1 — P31 input pin P31 output pin* RxD0 input pin Note: * When P31ODR = 1, it becomes NMOS open drain output. P30/TxD0 Switches as follows according to combinations of SCR TE bit of SCI0 and the P30DDR bit.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 10B I/O Ports (H8S/2695) 10B.4 Port 4 10B.4.1 Overview Port 4 is an 8-bit input-only port. Port 4 pins also function as A/D converter analog input pins (AN0 to AN7). Port 4 pin functions are the same in all operating modes. Figure 10B.3 shows the port 4 pin configuration.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 10B I/O Ports (H8S/2695) 10B.4.2 Register Configuration Table 10B.6 shows the port 4 register configuration. Port 4 is an input-only port, and does not have a data direction register or data register. Table 10B.6 Port 4 Registers Name Abbreviation R/W Initial Value Address* Port 4 register PORT4 R Undefined H'FFB3 Note: * Lower 16 bits of the address.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 10B I/O Ports (H8S/2695) 10B.5 Port 7 10B.5.1 Overview Port 7 is an 8-bit I/O port. Port 7 is a multipurpose port for the bus control output pins (CS4 to CS7), SCI I/O pins (SCK3, RxD3, and TxD3), and manual reset input pin (MRES). The pin functions for P77 to P74 are the same in all operating modes. P73 to P70 pin functions are switched according to operating mode. Figure 10B.4 shows the configuration for port 7 pins.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 10B I/O Ports (H8S/2695) 10B.5.2 Register Configuration Table 10B.7 shows the port 7 register configuration. Table 10B.7 Port 7 Register Configuration Name Abbreviation R/W Initial Value Address* Port 7 data direction register P7DDR W H'00 H'FE36 Port 7 data register P7DR R/W H'00 H'FF06 Port 7 register PORT7 R Undefined H'FFB6 Note: * Lower 16 bits of the address.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 10B I/O Ports (H8S/2695) Port 7 Data Register (P7DR) Bit : Initial value : R/W : 7 6 5 4 3 2 1 0 P77DR P76DR P75DR P74DR P73DR P72DR P71DR P70DR 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W P7DR is an 8-bit readable/writable register, which stores the output data of port 7 pins (P77 to P70). P7DR is initialized to H'00 by a power-on reset and in hardware standby mode.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 10B I/O Ports (H8S/2695) Table 10B.8 Port 7 Pin Functions Pin Selection Method and Pin Functions P77/TxD3 Switches as follows according to combinations of SCR TE bit of SCI3, and the P77DDR bit. TE 0 P77DDR Pin function P76/RxD3 0 1 — P77 input pin P77 output pin TxD3 output pin Switches as follows according to combinations of SCR RE bit of SCI3 and the P76DDR bit.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 10B I/O Ports (H8S/2695) Pin Selection Method and Pin Functions P73/CS7 Switches as follows according to combinations of operating mode and the P73DDR bit. Operating Mode P73DDR Pin function P72/CS6 Modes 4 to 6 0 1 0 1 P73 input pin CS7 output pin P73 input pin P73 output pin Switches as follows according to combinations of operating mode and the P72DDR bit.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 10B I/O Ports (H8S/2695) 10B.6 Port 9 10B.6.1 Overview Port 9 is an 8-bit input-only port. Port 9 pins also function as A/D converter analog input pins (AN8 to AN15). Port 9 pin functions are the same in all operating modes. Figure 10B.5 shows the port 9 pin configuration.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 10B I/O Ports (H8S/2695) 10B.6.2 Register Configuration Table 10B.9 shows the port 9 register configuration. Port 9 is an input-only port, and does not have a data direction register or data register. Table 10B.9 Port 9 Registers Name Abbreviation R/W Initial Value Address* Port 9 register PORT9 R Undefined H'FFB8 Note: * Lower 16 bits of the address.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 10B I/O Ports (H8S/2695) 10B.7 Port A 10B.7.1 Overview Port A is a 4-bit I/O port. Port A pins also function as SCI2 I/O pins (SCK2, RxD2, and TxD2) and address bus outputs. The pin functions change according to the operating mode. Port A has a built-in MOS input pull-up function that can be controlled by software. Figure 10B.6 shows the port A pin configuration.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 10B I/O Ports (H8S/2695) 10B.7.2 Register Configuration Table 10B.10 shows the port A register configuration. Table 10B.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 10B I/O Ports (H8S/2695) • Mode 7 Setting a PADDR bit to 1 makes the corresponding port A pin an output port, while clearing the bit to 0 makes the pin an input port.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 10B I/O Ports (H8S/2695) Port A MOS Pull-Up Control Register (PAPCR) Bit : 7 6 5 4 — — — — Initial value : Undefined Undefined Undefined Undefined R/W : — — — — 3 2 1 0 PA3PCR PA2PCR PA1PCR PA0PCR 0 0 0 0 R/W R/W R/W R/W PAPCR is an 8-bit readable/writable register that controls the MOS input pull-up function incorporated into port A on an individual bit basis.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 10B I/O Ports (H8S/2695) 10B.7.3 Pin Functions Port A pins also function as SCI input/output pins (TxD2, RxD2, SCK2) and address bus output pins (A19 to A16). Port A pin functions are shown in table 10B.11. Table 10B.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 10B I/O Ports (H8S/2695) Pin Selection Method and Pin Functions PA2/A18/RxD2 The pin function is switched as shown below according to the operating mode, bits AE3 to AE0 in PFCR, bit RE in SCR of SCI2, and bit PA2DDR.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 10B I/O Ports (H8S/2695) Pin Selection Method and Pin Functions PA0/A16 The pin function is switched as shown below according to the operating mode, bits AE3 to AE0 in PFCR, and bit PA0DDR.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 10B I/O Ports (H8S/2695) 10B.7.4 MOS Input Pull-Up Function Port A has a built-in MOS input pull-up function that can be controlled by software. MOS input pull-up can be specified as on or off on an individual bit basis.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 10B I/O Ports (H8S/2695) 10B.8 Port B 10B.8.1 Overview Port B is an 8-bit I/O port. Port B pins also function as TPU I/O pins (TIOCA3, TIOCB3, TIOCC3, TIOCD3, TIOCA4, TIOCB4, TIOCA5, and TIOCB5) and as address outputs; the pin functions change according to the operating mode. Port B has a built-in MOS input pull-up function that can be controlled by software. Figure 10B.7 shows the port B pin configuration.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 10B I/O Ports (H8S/2695) 10B.8.2 Register Configuration Table 10B.13 shows the port B register configuration. Table 10B.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 10B I/O Ports (H8S/2695) Port B Data Register (PBDR) Bit : Initial value : R/W : 7 6 5 4 3 2 1 0 PB7DR PB6DR PB5DR PB4DR PB3DR PB2DR PB1DR PB0DR 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W PBDR is an 8-bit readable/writable register that stores output data for the port B pins (PB7 to PB0). PBDR is initialized to H'00 by a power-on reset, and in hardware standby mode.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 10B I/O Ports (H8S/2695) Port B MOS Pull-Up Control Register (PBPCR) Bit : 7 6 5 4 3 2 1 0 PB7PCR PB6PCR PB5PCR PB4PCR PB3PCR PB2PCR PB1PCR PB0PCR Initial value : R/W : 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W PBPCR is an 8-bit readable/writable register that controls the MOS input pull-up function incorporated into port B on an individual bit basis.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 10B I/O Ports (H8S/2695) 10B.8.3 Pin Functions Port B pins also function as TPU output pins (TIOCA3, TIOCB3, TIOCC3, TIOCD3, TIOCA4, TIOCB4, TIOCC4, and TIOCD4) and address bus output pins (A15 to A8). Table 10B.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Pin PB7/A15/TIOCB5 Section 10B I/O Ports (H8S/2695) Selection Method and Pin Functions TPU Channel 5 Setting (2) MD3 to MD0 B'0000, B'01xx IOB3 to IOB0 B'0000 B'0100 B'1xxx (1) B'0001 to B'0011 (2) (2) B'0010 (1) (2) B'0011 — B'xx00 Other than B'xx00 B'0101 to B'0111 CCLR1, CCLR0 — — — — Other than B'10 B'10 Output function — Output compare output — — PWM mode 2 output — x: Don't care Note: TIOCB5 input w
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 10B I/O Ports (H8S/2695) Pin Selection Method and Pin Functions PB6/A14/TIOCA5 The function of this pin changes according to the operating mode and the setting of bits AE3 to AE0 in PFCR; the TPU5 settings of bits MD3 to MD0 in TMDR5, bits IOA3 to IOA0 in TIOR5, and the CCLR1 and CCLR0 bits in TCR5; and the setting of the PB6DDR bit.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Pin Section 10B I/O Ports (H8S/2695) Selection Method and Pin Functions PB5/A13/TIOCB4 The function of this pin changes according to the operating mode and the setting of bits AE3 to AE0 in PFCR; the TPU4 settings of bits MD3 to MD0 in TMDR4, bits IOB3 to IOB0 in TIOR4, and the CCLR1 and CCLR0 bits in TCR4; and the setting of the PB5DDR bit.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 10B I/O Ports (H8S/2695) Pin Selection Method and Pin Functions PB4/A12/TIOCA4 The function of this pin changes according to the operating mode and the setting of bits AE3 to AE0 in PFCR; the TPU4 settings of bits MD3 to MD0 in TMDR4, bits IOA3 to IOA0 in TIOR4, and the CCLR1 and CCLR0 bits in TCR4; and the setting of the PB4DDR bit.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Pin Section 10B I/O Ports (H8S/2695) Selection Method and Pin Functions PB3/A11/TIOCD3 The function of this pin changes according to the operating mode and the setting of bits AE3 to AE0 in PFCR; the TPU3 settings of bits MD3 to MD0 in TMDR3, bits IOD3 to IOD0 in TIORL3, and bits CCLR2 to CCLR0 in TCR3; and the setting of the PB3DDR bit.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 10B I/O Ports (H8S/2695) Pin Selection Method and Pin Functions PB2/A10/TIOCC3 The function of this pin changes according to the operating mode and the setting of bits AE3 to AE0 in PFCR; the TPU3 settings of bits MD3 to MD0 in TMDR3, bits IOC3 to IOC0 in TIORL3, and bits CCLR2 to CCLR0 in TCR3; and the setting of the PB2DDR bit.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 10B I/O Ports (H8S/2695) Pin Selection Method and Pin Functions PB1/A9/TIOCB3 The function of this pin changes according to the operating mode and the setting of bits AE3 to AE0 in PFCR; the TPU3 settings of bits MD3 to MD0 in TMDR3, bits IOB3 to IOB0 in TIORH3, and bits CCLR2 to CCLR0 in TCR3; and the setting of the PB1DDR bit.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 10B I/O Ports (H8S/2695) Pin Selection Method and Pin Functions PB0/A8/TIOCA3 The function of this pin changes according to the operating mode and the setting of bits AE3 to AE0 in PFCR; the TPU3 settings of bits MD3 to MD0 in TMDR3, bits IOA3 to IOA0 in TIORH3, and bits CCLR2 to CCLR0 in TCR3; and the setting of the PB0DDR bit.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 10B I/O Ports (H8S/2695) 10B.8.4 MOS Input Pull-Up Function Port B has a built-in MOS input pull-up function that can be controlled by software. MOS input pull-up can be specified as on or off on an individual bit basis. In modes 4 to 6, if a pin is in the input state in accordance with the settings in PFCR, in the TPU’s TIOR, and in DDR, setting the corresponding PBPCR bit to 1 turns on the MOS input pull-up for that pin.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 10B I/O Ports (H8S/2695) 10B.9 Port C 10B.9.1 Overview Port C is an 8-bit I/O port. Port C has an address bus output function. The pin functions change according to the operating mode. Port C has a built-in MOS input pull-up function that can be controlled by software. Figure 10B.8 shows the port C pin configuration.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 10B I/O Ports (H8S/2695) 10B.9.2 Register Configuration Table 10B.16 shows the port C register configuration. Table 10B.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 10B I/O Ports (H8S/2695) Port C Data Register (PCDR) Bit : Initial value : R/W : 7 6 5 4 3 2 1 0 PC7DR PC6DR PC5DR PC4DR PC3DR PC2DR PC1DR PC0DR 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W PCDR is an 8-bit readable/writable register that stores output data for the port C pins (PC7 to PC0). PCDR is initialized to H'00 by a power-on reset, and in hardware standby mode.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 10B I/O Ports (H8S/2695) Port C MOS Pull-Up Control Register (PCPCR) Bit : 7 6 5 4 3 2 1 0 PC7PCR PC6PCR PC5PCR PC4PCR PC3PCR PC2PCR PC1PCR PC0PCR Initial value : R/W : 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W PCPCR is an 8-bit readable/writable register that controls the MOS input pull-up function incorporated into port C on an individual bit basis.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 10B I/O Ports (H8S/2695) 10B.9.3 Pin Functions for Each Mode (1) Modes 4 and 5 In modes 4 and 5, port C pins function as address outputs automatically. Figure 10B.9 shows the port C pin functions. A7 (output) A6 (output) A5 (output) Port C A4 (output) A3 (output) A2 (output) A1 (output) A0 (output) Figure 10B.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Port C Section 10B I/O Ports (H8S/2695) PCDDR= 1 PCDDR= 0 A7 (output) PC7 (input) A6 (output) PC6 (input) A5 (output) PC5 (input) A4 (output) PC4 (input) A3 (output) PC3 (input) A2 (output) PC2 (input) A1 (output) PC1 (input) A0 (output) PC0 (input) Figure 10B.10 Port C Pin Functions (Mode 6) (3) Mode 7 In mode 7, port C pins function as I/O ports and I/O can be specified for each pin in bit units.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 10B I/O Ports (H8S/2695) 10B.9.4 MOS Input Pull-Up Function Port C has a built-in MOS input pull-up function that can be controlled by software. This MOS input pull-up function can be used in modes 6 and 7, and can be specified as on or off on an individual bit basis. In modes 6 and 7, when PCPCR is set to 1 in the input state by setting of PCDDR, the MOS input pull-up is set to ON.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 10B I/O Ports (H8S/2695) 10B.10 Port D 10B.10.1 Overview Port D is an 8-bit I/O port. Port D has a data bus I/O function, and the pin functions change according to the operating mode. Port D has a built-in MOS input pull-up function that can be controlled by software. Figure 10B.12 shows the port D pin configuration.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 10B I/O Ports (H8S/2695) 10B.10.2 Register Configuration Table 10B.18 shows the port D register configuration. Table 10B.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 10B I/O Ports (H8S/2695) Port D Data Register (PDDR) Bit : Initial value : R/W : 7 6 5 4 3 2 1 0 PD7DR PD6DR PD5DR PD4DR PD3DR PD2DR PD1DR PD0DR 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W PDDR is an 8-bit readable/writable register that stores output data for the port D pins (PD7 to PD0). PDDR is initialized to H'00 by a power-on reset, and in hardware standby mode.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 10B I/O Ports (H8S/2695) Port D MOS Pull-Up Control Register (PDPCR) Bit : 7 6 5 4 3 2 1 0 PD7PCR PD6PCR PD5PCR PD4PCR PD3PCR PD2PCR PD1PCR PD0PCR Initial value : R/W : 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W PDPCR is an 8-bit readable/writable register that controls the MOS input pull-up function incorporated into port D on an individual bit basis.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 10B I/O Ports (H8S/2695) Port D pin functions in mode 7 are shown in figure 10B.14. PD7 (I/O) PD6 (I/O) PD5 (I/O) Port D PD4 (I/O) PD3 (I/O) PD2 (I/O) PD1 (I/O) PD0 (I/O) Figure 10B.14 Port D Pin Functions (Mode 7) 10B.10.4 MOS Input Pull-Up Function Port D has a built-in MOS input pull-up function that can be controlled by software.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 10B I/O Ports (H8S/2695) 10B.11 Port E 10B.11.1 Overview Port E is an 8-bit I/O port. Port E has a data bus I/O function, and the pin functions change according to the operating mode and whether 8-bit or 16-bit bus mode is selected. Port E has a built-in MOS input pull-up function that can be controlled by software. Figure 10B.15 shows the port E pin configuration.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 10B I/O Ports (H8S/2695) 10B.11.2 Register Configuration Table 10B.20 shows the port E register configuration. Table 10B.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 10B I/O Ports (H8S/2695) Port E Data Register (PEDR) Bit : Initial value : R/W : 7 6 5 4 3 2 1 0 PE7DR PE6DR PE5DR PE4DR PE3DR PE2DR PE1DR PE0DR 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W PEDR is an 8-bit readable/writable register that stores output data for the port E pins (PE7 to PE0). PEDR is initialized to H'00 by a power-on reset, and in hardware standby mode.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 10B I/O Ports (H8S/2695) PEPCR is an 8-bit readable/writable register that controls the MOS input pull-up function incorporated into port E on an individual bit basis. When a PEDDR bit is cleared to 0 (input port setting) with 8-bit bus mode selected in modes 4, 5, or 6, or in mode 7, setting the corresponding PEPCR bit to 1 turns on the MOS input pull-up for the corresponding pin.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 10B I/O Ports (H8S/2695) PE7 (I/O) PE6 (I/O) PE5 (I/O) Port E PE4 (I/O) PE3 (I/O) PE2 (I/O) PE1 (I/O) PE0 (I/O) Figure 10B.17 Port E Pin Functions (Mode 7) 10B.11.4 MOS Input Pull-Up Function Port E has a built-in MOS input pull-up function that can be controlled by software.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 10B I/O Ports (H8S/2695) 10B.12 Port F 10B.12.1 Overview Port F is an 8-bit I/O port. Port F pins also function as external interrupt input pins (IRQ2 and IRQ3), A/D trigger input pin (ADTRG), bus control signal input/output pins (AS, RD, HWR, LWR, WAIT, BREQO, BREQ, and BACK), and the system clock (φ) output pin. Figure 10B.18 shows the port F pin configuration.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 10B I/O Ports (H8S/2695) 10B.12.2 Register Configuration Table 10B.22 shows the port F register configuration. Table 10B.22 Port F Registers Name Abbreviation R/W Initial Value 1 Address* Port F data direction register PFDDR W 2 H'80/H'00* H'FE3E Port F data register PFDR R/W H'00 H'FF0E Port F register PORTF R Undefined H'FFBE Notes: 1. Lower 16 bits of the address. 2. Initial value depends on the mode.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 10B I/O Ports (H8S/2695) Pins PF2 to PF0 are designated as bus control input/output pins (WAIT, BREQO, BACK, and BREQ) by means of bus controller settings. At other times, setting a PFDDR bit to 1 makes the corresponding port F pin an output port, while clearing the bit to 0 makes the pin an input port.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 10B I/O Ports (H8S/2695) 10B.12.3 Pin Functions Port F pins also function as external interrupt input pins (IRQ2 and IRQ3), A/D trigger input pin (ADTRG), bus control signal input/output pins (AS, RD, HWR, LWR, WAIT, BREQO, BREQ, and BACK), and the system clock (φ) output pin. The pin functions differ between modes 4 to 6, and mode 7. Port F pin functions are shown in table 10B.23. Table 10B.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Pin Section 10B I/O Ports (H8S/2695) Selection Method and Pin Functions PF3/LWR/ADTRG/ The pin function is switched as shown below according to the operating mode, IRQ3 the bus mode, A/D converter bits TRGS1 and TRGS0, and bit PF3DDR.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 10B I/O Ports (H8S/2695) Pin Selection Method and Pin Functions PF0/BREQ/IRQ2 The pin function is switched as shown below according to the combination of the operating mode, and bits BRLE and PF0DDR. Operating Mode Modes 4 to 6 BRLE 0 PF0DDR Pin function Mode 7 1 — 0 1 — 0 1 PF0 input pin PF0 output pin BREQ input pin PF0 input pin PF0 output pin IRQ2 input pin 10B.13 Port G 10B.13.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 10B I/O Ports (H8S/2695) 10B.13.2 Register Configuration Table 10B.24 shows the port G register configuration. Table 10B.24 Port G Registers Name Abbreviation R/W 2 1 Initial Value* Address* Port G data direction register PGDDR W 3 H'10/H'00* H'FE3F Port G data register PGDR R/W H'00 H'FF0F Port G register PORTG R Undefined H'FFBF Notes: 1. Lower 16 bits of the address. 2. Value of bits 4 to 0. 3.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 10B I/O Ports (H8S/2695) When PGDDR is set to 1, the PG0 pin functions as an output port, and when PGDDR is cleared to 0, it functions as an input port. • Mode 7 PGDDR to 1 it becomes an output port, and by clearing it to 0 it becomes an input port.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 10B I/O Ports (H8S/2695) In power-on reset or hardware standby mode, port G is determined by the pin state because PGDDR and PGDR are initialized. In manual reset or software standby mode, the last state is retained. 10B.13.3 Pin Functions Port G is used also as external interrupt input pins (IRQ6 and IRQ7) and bus control signal output pins (CS0 to CS3). The pin functions are different between modes 4 and 6, and mode 7.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 10B I/O Ports (H8S/2695) Pin Selection Method and Pin Functions PG1/CS3/ IRQ7 The pin function is switched as shown below according to the operating mode and bits OES and PG1DDR in BCRL.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 11 16-Bit Timer Pulse Unit (TPU) Section 11 16-Bit Timer Pulse Unit (TPU) 11.1 Overview The H8S/2633 Group has an on-chip 16-bit timer pulse unit (TPU) that comprises six 16-bit timer channels. 11.1.
Section 11 16-Bit Timer Pulse Unit (TPU) H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 • 26 interrupt sources ⎯ For channels 0 and 3, four compare match/input capture dual-function interrupts and one overflow interrupt can be requested independently ⎯ For channels 1, 2, 4, and 5, two compare match/input capture dual-function interrupts, one overflow interrupt, and one underflow interrupt can be requested independently • Automatic transfer of register data ⎯ Block transfer, 1-word dat
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 11 16-Bit Timer Pulse Unit (TPU) Table 11.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 11 16-Bit Timer Pulse Unit (TPU) Item Channel 0 Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 DMAC TGR0A TGR1A TGR2A TGR3A TGR4A TGR5A activation* compare compare compare compare compare compare match or input match or input match or input match or input match or input match or input capture capture capture capture capture capture DTC TGR compare TGR compare TGR compare TGR compare TGR compare TGR compare activation* matc
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 11.1.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 11 16-Bit Timer Pulse Unit (TPU) 11.1.3 Pin Configuration Table 11.2 summarizes the TPU pins. Table 11.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 11 16-Bit Timer Pulse Unit (TPU) Channel Name Symbol I/O Function 3 Input capture/out compare match A3 TIOCA3 I/O TGR3A input capture input/output compare output/PWM output pin Input capture/out compare match B3 TIOCB3 I/O TGR3B input capture input/output compare output/PWM output pin Input capture/out compare match C3 TIOCC3 I/O TGR3C input capture input/output compare output/PWM output pin Input capture/out co
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 11 16-Bit Timer Pulse Unit (TPU) 11.1.4 Register Configuration Table 11.3 summarizes the TPU registers. Table 11.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 11 16-Bit Timer Pulse Unit (TPU) Channel Name Abbreviation R/W Initial Value Address* 3 Timer control register 3 TCR3 R/W H'00 H'FE80 Timer mode register 3 TMDR3 R/W H'C0 H'FE81 Timer I/O control register 3H TIOR3H R/W H'00 H'FE82 Timer I/O control register 3L TIOR3L R/W H'00 H'FE83 Timer interrupt enable register 3 TIER3 R/W H'FE84 Timer status register 3 TSR3 H'40 2 * R/(W) H'C0 4 5 All 1 H'
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 11 16-Bit Timer Pulse Unit (TPU) 11.2 Register Descriptions 11.2.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 11 16-Bit Timer Pulse Unit (TPU) Bits 7, 6, and 5—Counter Clear 2, 1, and 0 (CCLR2, CCLR1, CCLR0): These bits select the TCNT counter clearing source.
Section 11 16-Bit Timer Pulse Unit (TPU) H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Bits 4 and 3—Clock Edge 1 and 0 (CKEG1, CKEG0): These bits select the input clock edge. When the input clock is counted using both edges, the input clock period is halved (e.g. φ/4 both edges = φ/2 rising edge). If phase counting mode is used on channels 1, 2, 4, and 5, this setting is ignored and the phase counting mode setting has priority.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 11 16-Bit Timer Pulse Unit (TPU) Bit 2 Bit 1 Bit 0 Channel TPSC2 TPSC1 TPSC0 Description 0 0 0 0 Internal clock: counts on φ/1 1 Internal clock: counts on φ/4 0 Internal clock: counts on φ/16 1 Internal clock: counts on φ/64 0 External clock: counts on TCLKA pin input 1 External clock: counts on TCLKB pin input 1 1 0 1 (Initial value) 0 External clock: counts on TCLKC pin input 1 External clock: cou
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 11 16-Bit Timer Pulse Unit (TPU) Bit 2 Bit 1 Bit 0 Channel TPSC2 TPSC1 TPSC0 Description 3 0 0 0 Internal clock: counts on φ/1 1 Internal clock: counts on φ/4 0 Internal clock: counts on φ/16 1 Internal clock: counts on φ/64 0 External clock: counts on TCLKA pin input 1 Internal clock: counts on φ/1024 0 Internal clock: counts on φ/256 1 Internal clock: counts on φ/4096 1 1 0 1 (Initial value) Bit 2
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 11.2.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 11 16-Bit Timer Pulse Unit (TPU) Bit 5 BFB Description 0 TGRB operates normally 1 TGRB and TGRD used together for buffer operation (Initial value) Bit 4—Buffer Operation A (BFA): Specifies whether TGRA is to operate in the normal way, or TGRA and TGRC are to be used together for buffer operation. When TGRC is used as a buffer register, TGRC input capture/output compare is not generated.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 11.2.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 11 16-Bit Timer Pulse Unit (TPU) Bits 7 to 4— I/O Control B3 to B0 (IOB3 to IOB0) I/O Control D3 to D0 (IOD3 to IOD0): Bits IOB3 to IOB0 specify the function of TGRB. Bits IOD3 to IOD0 specify the function of TGRD.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 11 16-Bit Timer Pulse Unit (TPU) Bit 7 Bit 6 Bit 5 Bit 4 Channel IOD3 IOD2 IOD1 IOD0 Description 0 0 0 0 0 1 1 0 Output disabled TGR0D is output Initial output is 0 compare output 2 register* 1 1 0 1 Output disabled 1 Initial output is 1 output 1 1 0 0 0 1 1 1 * * * 0 output at compare match 1 output at compare match Toggle output at compare match 0 0 (Initial value) 0 output at compare match 1 output
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 11 16-Bit Timer Pulse Unit (TPU) Bit 7 Bit 6 Bit 5 Bit 4 Channel IOB3 IOB2 IOB1 IOB0 Description 1 0 0 0 0 1 1 0 TGR1B is output compare register Output disabled Initial output is 0 0 output at compare match output 1 output at compare match 1 1 0 1 Toggle output at compare match 0 Output disabled 1 Initial output is 1 output 0 1 1 0 0 0 1 1 1 * * * (Initial value) 0 output at compare match 1 output at c
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 11 16-Bit Timer Pulse Unit (TPU) Bit 7 Bit 6 Bit 5 Bit 4 Channel IOB3 IOB2 IOB1 IOB0 Description 3 0 0 0 0 1 1 0 TGR3B is output compare register Output disabled Initial output is 0 output 1 1 0 1 0 0 0 Output disabled 1 Initial output is 1 output 0 0 1 1 Note: 1 * * * 0 output at compare match 1 output at compare match Toggle output at compare match 1 1 (Initial value) 0 output at compare match 1 o
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 11 16-Bit Timer Pulse Unit (TPU) Bit 7 Bit 6 Bit 5 Bit 4 Channel IOD3 IOD2 IOD1 IOD0 Description 3 0 0 0 0 1 1 0 Output disabled TGR3D is output Initial output is 0 compare output 2 register* 1 1 0 1 Output disabled 1 Initial output is 1 output 1 1 0 0 0 1 1 1 * * * 0 output at compare match 1 output at compare match Toggle output at compare match 0 0 (Initial value) 0 output at compare match 1 output at
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 11 16-Bit Timer Pulse Unit (TPU) Bit 7 Bit 6 Bit 5 Bit 4 Channel IOB3 IOB2 IOB1 IOB0 Description 4 0 0 0 0 1 1 0 TGR4B is output compare register Output disabled Initial output is 0 output 1 1 0 1 0 0 0 Output disabled 1 Initial output is 1 output 0 0 1 1 1 * * * 0 output at compare match 1 output at compare match Toggle output at compare match 1 1 (Initial value) 0 output at compare match 1 output at
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 11 16-Bit Timer Pulse Unit (TPU) Bits 3 to 0— I/O Control A3 to A0 (IOA3 to IOA0) I/O Control C3 to C0 (IOC3 to IOC0): IOA3 to IOA0 specify the function of TGRA. IOC3 to IOC0 specify the function of TGRC.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 11 16-Bit Timer Pulse Unit (TPU) Bit 3 Bit 2 Bit 1 Bit 0 Channel IOC3 IOC2 IOC1 IOC0 Description 0 0 0 0 0 1 1 0 Output disabled TGR0C is output Initial output is 0 compare output 1 register* 1 1 0 1 Output disabled 1 Initial output is 1 output 1 1 0 0 0 1 1 Note: 1 * * * 0 output at compare match 1 output at compare match Toggle output at compare match 0 0 (Initial value) 0 output at compare match 1
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 11 16-Bit Timer Pulse Unit (TPU) Bit 3 Bit 2 Bit 1 Bit 0 Channel IOA3 IOA2 IOA1 IOA0 Description 1 0 0 0 0 1 1 0 TGR1A is output compare register Output disabled Initial output is 0 output 0 1 0 Output disabled 1 Initial output is 1 output 0 1 1 0 0 0 1 1 1 * * * 0 output at compare match 1 output at compare match Toggle output at compare match 1 1 (Initial value) 0 output at compare match 1 output at co
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 11 16-Bit Timer Pulse Unit (TPU) Bit 3 Bit 2 Bit 1 Bit 0 Channel IOA3 IOA2 IOA1 IOA0 Description 3 0 0 0 0 1 1 0 TGR3A is output compare register Output disabled Initial output is 0 output 1 1 0 1 0 0 0 Output disabled 1 Initial output is 1 output 0 0 1 1 1 * * * 0 output at compare match 1 output at compare match Toggle output at compare match 1 1 (Initial value) 0 output at compare match 1 output a
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 11 16-Bit Timer Pulse Unit (TPU) Bit 3 Bit 2 Bit 1 Bit 0 Channel IOC3 IOC2 IOC1 IOC0 Description 3 0 0 0 0 1 1 0 TGR3C Output disabled is output Initial output is 0 compare output 1 register* 0 0 Output disabled 1 1 0 Initial output is 1 output 1 1 0 0 0 1 1 Note: 1 * * * 0 output at compare match 1 output at compare match Toggle output at compare match 1 1 (Initial value) 0 output at compare match 1 out
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 11 16-Bit Timer Pulse Unit (TPU) Bit 3 Bit 2 Bit 1 Bit 0 Channel IOA3 IOA2 IOA1 IOA0 Description 4 0 0 0 0 1 1 0 TGR4A is output compare register Output disabled Initial output is 0 output 1 1 0 1 0 0 0 Output disabled 1 Initial output is 1 output 0 0 1 1 1 * * * 0 output at compare match 1 output at compare match Toggle output at compare match 1 1 (Initial value) 0 output at compare match 1 output at
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 11 16-Bit Timer Pulse Unit (TPU) 11.2.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 11 16-Bit Timer Pulse Unit (TPU) Bit 7—A/D Conversion Start Request Enable (TTGE): Enables or disables generation of A/D conversion start requests by TGRA input capture/compare match. Bit 7 TTGE Description 0 A/D conversion start request generation disabled 1 A/D conversion start request generation enabled (Initial value) Bit 6—Reserved: This bit is always read as 1 and cannot be modified.
Section 11 16-Bit Timer Pulse Unit (TPU) H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Bit 2—TGR Interrupt Enable C (TGIEC): Enables or disables interrupt requests (TGIC) by the TGFC bit when the TGFC bit in TSR is set to 1 in channels 0 and 3. In channels 1, 2, 4, and 5, bit 2 is reserved. It is always read as 0 and cannot be modified.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 11.2.5 Section 11 16-Bit Timer Pulse Unit (TPU) Timer Status Register (TSR) Channel 0: TSR0 Channel 3: TSR3 Bit : 7 6 5 4 3 2 1 0 — — — TCFV TGFD TGFC TGFB TGFA 1 1 0 0 0 0 0 0 — R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* Initial value : R/W : — — Note: * Only 0 can be written, for flag clearing.
Section 11 16-Bit Timer Pulse Unit (TPU) H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Bit 7—Count Direction Flag (TCFD): Status flag that shows the direction in which TCNT counts in channels 1, 2, 4, and 5. In channels 0 and 3, bit 7 is reserved. It is always read as 1 and cannot be modified. Bit 7 TCFD Description 0 TCNT counts down 1 TCNT counts up (Initial value) Bit 6—Reserved: This bit is always read as 1 and cannot be modified.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 11 16-Bit Timer Pulse Unit (TPU) Bit 3—Input Capture/Output Compare Flag D (TGFD): Status flag that indicates the occurrence of TGRD input capture or compare match in channels 0 and 3. In channels 1, 2, 4, and 5, bit 3 is reserved. It is always read as 0 and cannot be modified.
Section 11 16-Bit Timer Pulse Unit (TPU) H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Bit 1—Input Capture/Output Compare Flag B (TGFB): Status flag that indicates the occurrence of TGRB input capture or compare match.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 11.2.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 11 16-Bit Timer Pulse Unit (TPU) 11.2.7 Timer General Register (TGR) Bit : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value : 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R/W : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W The TGR registers are 16-bit registers with a dual function as output compare and input capture registers.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 11.2.8 Section 11 16-Bit Timer Pulse Unit (TPU) Timer Start Register (TSTR) Bit : 7 6 5 4 3 2 1 0 — — CST5 CST4 CST3 CST2 CST1 CST0 Initial value : 0 0 0 0 0 0 0 0 R/W — — R/W R/W R/W R/W R/W R/W : TSTR is an 8-bit readable/writable register that selects operation/stoppage for channels 0 to 5. TSTR is initialized to H'00 by a reset, and in hardware standby mode.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 11 16-Bit Timer Pulse Unit (TPU) 11.2.9 Timer Synchro Register (TSYR) Bit : 7 6 5 4 3 2 1 0 — — SYNC5 SYNC4 SYNC3 SYNC2 SYNC1 SYNC0 Initial value : 0 0 0 0 0 0 0 0 R/W — — R/W R/W R/W R/W R/W R/W : TSYR is an 8-bit readable/writable register that selects independent operation or synchronous operation for the channels 0 to 5 TCNT counters.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 11 16-Bit Timer Pulse Unit (TPU) 11.2.10 Module Stop Control Register A (MSTPCRA) Bit : 7 6 5 4 3 2 1 0 MSTPA7 MSTPA6 MSTPA5 MSTPA4 MSTPA3 MSTPA2 MSTPA1 MSTPA0 Initial value : R/W : 0 0 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W MSTPCRA is an 8-bit readable/writable register that performs module stop mode control.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 11 16-Bit Timer Pulse Unit (TPU) 11.3 Interface to Bus Master 11.3.1 16-Bit Registers TCNT and TGR are 16-bit registers. As the data bus to the bus master is 16 bits wide, these registers can be read and written to in 16-bit units. These registers cannot be read or written to in 8-bit units; 16-bit access must always be used. An example of 16-bit register access operation is shown in figure 11.2.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 11 16-Bit Timer Pulse Unit (TPU) Examples of 8-bit register access operation are shown in figures 11.3, 11.4, and 11.5. Internal data bus H Bus master L Module data bus Bus interface TCR Figure 11.3 8-Bit Register Access Operation [Bus Master ↔ TCR (Upper 8 Bits)] Internal data bus H Bus master L Module data bus Bus interface TMDR Figure 11.
Section 11 16-Bit Timer Pulse Unit (TPU) 11.4 Operation 11.4.1 Overview H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Operation in each mode is outlined below. Normal Operation: Each channel has a TCNT and TGR register. TCNT performs up-counting, and is also capable of free-running operation, synchronous counting, and external event counting. Each TGR can be used as an input capture register or output compare register.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 11.4.2 Section 11 16-Bit Timer Pulse Unit (TPU) Basic Functions Counter Operation When one of bits CST0 to CST5 is set to 1 in TSTR, the TCNT counter for the corresponding channel starts counting. TCNT can operate as a free-running counter, periodic counter, and so on. Example of count operation setting procedure: Figure 11.6 shows an example of the count operation setting procedure.
Section 11 16-Bit Timer Pulse Unit (TPU) H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Free-running count operation and periodic count operation: Immediately after a reset, the TPU’s TCNT counters are all designated as free-running counters. When the relevant bit in TSTR is set to 1 the corresponding TCNT counter starts up-count operation as a free-running counter. When TCNT overflows (from H'FFFF to H'0000), the TCFV bit in TSR is set to 1.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 11 16-Bit Timer Pulse Unit (TPU) Figure 11.8 illustrates periodic counter operation. TCNT value TGR Counter cleared by TGR compare match H'0000 Time CST bit Flag cleared by software or DTC*/DMAC* activation TGF Note: * DMAC and DTC functions are not available in the H8S/2695. Figure 11.8 Periodic Counter Operation R01UH0166EJ0600 Rev. 6.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 11 16-Bit Timer Pulse Unit (TPU) Waveform Output by Compare Match The TPU can perform 0, 1, or toggle output from the corresponding output pin using compare match. Example of setting procedure for waveform output by compare match: Figure 11.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 11 16-Bit Timer Pulse Unit (TPU) Examples of waveform output operation: Figure 11.10 shows an example of 0 output/1 output. In this example TCNT has been designated as a free-running counter, and settings have been made so that 1 is output by compare match A, and 0 is output by compare match B. When the set level and the pin level coincide, the pin level does not change.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 11 16-Bit Timer Pulse Unit (TPU) Input Capture Function The TCNT value can be transferred to TGR on detection of the TIOC pin input edge. Rising edge, falling edge, or both edges can be selected as the detected edge. For channels 0, 1, 3, and 4, it is also possible to specify another channel’s counter input clock or compare match signal as the input capture source.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 11 16-Bit Timer Pulse Unit (TPU) Example of input capture operation: Figure 11.13 shows an example of input capture operation. In this example both rising and falling edges have been selected as the TIOCA pin input capture input edge, falling edge has been selected as the TIOCB pin input capture input edge, and counter clearing by TGRB input capture has been designated for TCNT.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 11 16-Bit Timer Pulse Unit (TPU) Example of Synchronous Operation Setting Procedure: Figure 11.14 shows an example of the synchronous operation setting procedure.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 11 16-Bit Timer Pulse Unit (TPU) Example of Synchronous Operation: Figure 11.15 shows an example of synchronous operation. In this example, synchronous operation and PWM mode 1 have been designated for channels 0 to 2, TGR0B compare match has been set as the channel 0 counter clearing source, and synchronous clearing has been set for the channel 1 and 2 counter clearing source.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 11 16-Bit Timer Pulse Unit (TPU) 11.4.4 Buffer Operation Buffer operation, provided for channels 0 and 3, enables TGRC and TGRD to be used as buffer registers. Buffer operation differs depending on whether TGR has been designated as an input capture register or as a compare match register. Table 11.5 shows the register combinations used in buffer operation. Table 11.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 11 16-Bit Timer Pulse Unit (TPU) • When TGR is an input capture register When input capture occurs, the value in TCNT is transferred to TGR and the value previously held in the timer general register is transferred to the buffer register. This operation is illustrated in figure 11.17. Input capture signal Timer general register Buffer register TCNT Figure 11.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 11 16-Bit Timer Pulse Unit (TPU) Examples of Buffer Operation • When TGR is an output compare register Figure 11.19 shows an operation example in which PWM mode 1 has been designated for channel 0, and buffer operation has been designated for TGRA and TGRC. The settings used in this example are TCNT clearing by compare match B, 1 output at compare match A, and 0 output at compare match B.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 11 16-Bit Timer Pulse Unit (TPU) • When TGR is an input capture register Figure 11.20 shows an operation example in which TGRA has been designated as an input capture register, and buffer operation has been designated for TGRA and TGRC. Counter clearing by TGRA input capture has been set for TCNT, and both rising and falling edges have been selected as the TIOCA pin input capture input edge.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 11 16-Bit Timer Pulse Unit (TPU) 11.4.5 Cascaded Operation In cascaded operation, two 16-bit counters for different channels are used together as a 32-bit counter. This function works by counting the channel 1 (channel 4) counter clock upon overflow/underflow of TCNT2 (TCNT5) as set in bits TPSC2 to TPSC0 in TCR. Underflow occurs only when the lower 16-bit TCNT is in phase-counting mode. Table 11.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 11 16-Bit Timer Pulse Unit (TPU) Examples of Cascaded Operation: Figure 11.22 illustrates the operation when counting upon TCNT2 overflow/underflow has been set for TCNT1, TGR1A and TGR2A have been designated as input capture registers, and TIOC pin rising edge has been selected.
Section 11 16-Bit Timer Pulse Unit (TPU) 11.4.6 H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 PWM Modes In PWM mode, PWM waveforms are output from the output pins. 0, 1, or toggle output can be selected as the output level in response to compare match of each TGR. Designating TGR compare match as the counter clearing source enables the period to be set in that register. All channels can be designated for PWM mode independently. Synchronous operation is also possible.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 11 16-Bit Timer Pulse Unit (TPU) Table 11.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 11 16-Bit Timer Pulse Unit (TPU) Example of PWM Mode Setting Procedure: Figure 11.24 shows an example of the PWM mode setting procedure. PWM mode Select counter clock [1] [1] Select the counter clock with bits TPSC2 to TPSC0 in TCR. At the same time, select the input clock edge with bits CKEG1 and CKEG0 in TCR. [2] Use bits CCLR2 to CCLR0 in TCR to select the TGR to be used as the TCNT clearing source.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 11 16-Bit Timer Pulse Unit (TPU) Examples of PWM Mode Operation: Figure 11.25 shows an example of PWM mode 1 operation. In this example, TGRA compare match is set as the TCNT clearing source, 0 is set for the TGRA initial output value and output value, and 1 is set as the TGRB output value. In this case, the value set in TGRA is used as the period, and the values set in TGRB registers as the duty.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 11 16-Bit Timer Pulse Unit (TPU) Figure 11.26 shows an example of PWM mode 2 operation. In this example, synchronous operation is designated for channels 0 and 1, TGR1B compare match is set as the TCNT clearing source, and 0 is set for the initial output value and 1 for the output value of the other TGR registers (TGR0A to TGR0D, TGR1A), to output a 5-phase PWM waveform.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 11 16-Bit Timer Pulse Unit (TPU) Figure 11.27 shows examples of PWM waveform output with 0% duty and 100% duty in PWM mode.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 11 16-Bit Timer Pulse Unit (TPU) 11.4.7 Phase Counting Mode In phase counting mode, the phase difference between two external clock inputs is detected and TCNT is incremented/decremented accordingly. This mode can be set for channels 1, 2, 4, and 5.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 11 16-Bit Timer Pulse Unit (TPU) Examples of Phase Counting Mode Operation: In phase counting mode, TCNT counts up or down according to the phase difference between two external clocks. There are four modes, according to the count conditions. • Phase counting mode 1 Figure 11.29 shows an example of phase counting mode 1 operation, and table 11.9 summarizes the TCNT up/down-count conditions.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 11 16-Bit Timer Pulse Unit (TPU) • Phase counting mode 2 Figure 11.30 shows an example of phase counting mode 2 operation, and table 11.10 summarizes the TCNT up/down-count conditions. TCLKA (Channels 1 and 5) TCLKC (Channels 2 and 4) TCLKB (Channels 1 and 5) TCLKD (Channels 2 and 4) TCNT value Up-count Down-count Time Figure 11.30 Example of Phase Counting Mode 2 Operation Table 11.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 11 16-Bit Timer Pulse Unit (TPU) • Phase counting mode 3 Figure 11.31 shows an example of phase counting mode 3 operation, and table 11.11 summarizes the TCNT up/down-count conditions. TCLKA (channels 1 and 5) TCLKC (channels 2 and 4) TCLKB (channels 1 and 5) TCLKD (channels 2 and 4) TCNT value Up-count Down-count Time Figure 11.31 Example of Phase Counting Mode 3 Operation Table 11.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 11 16-Bit Timer Pulse Unit (TPU) • Phase counting mode 4 Figure 11.32 shows an example of phase counting mode 4 operation, and table 11.12 summarizes the TCNT up/down-count conditions. TCLKA (channels 1 and 5) TCLKC (channels 2 and 4) TCLKB (channels 1 and 5) TCLKD (channels 2 and 4) TCNT value Up-count Down-count Time Figure 11.32 Example of Phase Counting Mode 4 Operation Table 11.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 11 16-Bit Timer Pulse Unit (TPU) Phase Counting Mode Application Example: Figure 11.33 shows an example in which phase counting mode is designated for channel 1, and channel 1 is coupled with channel 0 to input servo motor 2-phase encoder pulses in order to detect the position or speed. Channel 1 is set to phase counting mode 1, and the encoder pulse A-phase and B-phase are input to TCLKA and TCLKB.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 11 16-Bit Timer Pulse Unit (TPU) Channel 1 TCLKA TCLKB Edge detection circuit TCNT1 TGR1A (speed period capture) TGR1B (position period capture) TCNT0 + TGR0A (speed control period) – + TGR0C (position control period) – TGR0B (pulse width capture) TGR0D (buffer operation) Channel 0 Figure 11.33 Phase Counting Mode Application Example Page 614 of 1434 R01UH0166EJ0600 Rev. 6.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 11.5 Interrupts 11.5.1 Interrupt Sources and Priorities Section 11 16-Bit Timer Pulse Unit (TPU) There are three kinds of TPU interrupt source: TGR input capture/compare match, TCNT overflow, and TCNT underflow. Each interrupt source has its own status flag and enable/disabled bit, allowing generation of interrupt request signals to be enabled or disabled individually.
Section 11 16-Bit Timer Pulse Unit (TPU) Table 11.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 11 16-Bit Timer Pulse Unit (TPU) Input Capture/Compare Match Interrupt: An interrupt is requested if the TGIE bit in TIER is set to 1 when the TGF flag in TSR is set to 1 by the occurrence of a TGR input capture/compare match on a particular channel. The interrupt request is cleared by clearing the TGF flag to 0.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 11 16-Bit Timer Pulse Unit (TPU) 11.6 Operation Timing 11.6.1 Input/Output Timing TCNT Count Timing: Figure 11.34 shows TCNT count timing in internal clock operation, and figure 11.35 shows TCNT count timing in external clock operation. φ Internal clock Rising edge Falling edge TCNT input clock TCNT N–1 N N+1 N+2 Figure 11.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 11 16-Bit Timer Pulse Unit (TPU) Output Compare Output Timing: A compare match signal is generated in the final state in which TCNT and TGR match (the point at which the count value matched by TCNT is updated). When a compare match signal is generated, the output value set in TIOR is output at the output compare output pin (TIOC pin).
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 11 16-Bit Timer Pulse Unit (TPU) Timing for Counter Clearing by Compare Match/Input Capture: Figure 11.38 shows the timing when counter clearing by compare match occurrence is specified, and figure 11.39 shows the timing when counter clearing by input capture occurrence is specified. φ Compare match signal Counter clear signal TCNT N TGR N H'0000 Figure 11.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 11 16-Bit Timer Pulse Unit (TPU) Buffer Operation Timing: Figures 11.40 and 11.41 show the timing in buffer operation. φ n TCNT n+1 Compare match signal TGRA, TGRB n TGRC, TGRD N N Figure 11.40 Buffer Operation Timing (Compare Match) φ Input capture signal TCNT N TGRA, TGRB n TGRC, TGRD N+1 N N+1 n N Figure 11.41 Buffer Operation Timing (Input Capture) R01UH0166EJ0600 Rev. 6.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 11 16-Bit Timer Pulse Unit (TPU) 11.6.2 Interrupt Signal Timing TGF Flag Setting Timing in Case of Compare Match: Figure 11.42 shows the timing for setting of the TGF flag in TSR by compare match occurrence, and TGI interrupt request signal timing. φ TCNT input clock TCNT N TGR N N+1 Compare match signal TGF flag TGI interrupt Figure 11.42 TGI Interrupt Timing (Compare Match) Page 622 of 1434 R01UH0166EJ0600 Rev. 6.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 11 16-Bit Timer Pulse Unit (TPU) TGF Flag Setting Timing in Case of Input Capture: Figure 11.43 shows the timing for setting of the TGF flag in TSR by input capture occurrence, and TGI interrupt request signal timing. φ Input capture signal N TCNT TGR N TGF flag TGI interrupt Figure 11.43 TGI Interrupt Timing (Input Capture) R01UH0166EJ0600 Rev. 6.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 11 16-Bit Timer Pulse Unit (TPU) TCFV Flag/TCFU Flag Setting Timing: Figure 11.44 shows the timing for setting of the TCFV flag in TSR by overflow occurrence, and TCIV interrupt request signal timing. Figure 11.45 shows the timing for setting of the TCFU flag in TSR by underflow occurrence, and TCIU interrupt request signal timing.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 11 16-Bit Timer Pulse Unit (TPU) Status Flag Clearing Timing: After a status flag is read as 1 by the CPU, it is cleared by writing 0 to it. When the DTC* or DMAC* is activated, the flag is cleared automatically. Figure 11.46 shows the timing for status flag clearing by the CPU, and figure 11.47 shows the timing for status flag clearing by the DTC* or DMAC*. Note: * DMAC and DTC functions are not available in the H8S/2695.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 11 16-Bit Timer Pulse Unit (TPU) 11.7 Usage Notes Note that the kinds of operation and contention described below occur during TPU operation. Input Clock Restrictions: The input clock pulse width must be at least 1.5 states in the case of single-edge detection, and at least 2.5 states in the case of both-edge detection. The TPU will not operate properly with a narrower pulse width.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 11 16-Bit Timer Pulse Unit (TPU) Contention between TCNT Write and Clear Operations: If the counter clear signal is generated in the T2 state of a TCNT write cycle, TCNT clearing takes precedence and the TCNT write is not performed. Figure 11.49 shows the timing in this case. TCNT write cycle T1 T2 φ TCNT address Address Write signal Counter clear signal N TCNT H'0000 Figure 11.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 11 16-Bit Timer Pulse Unit (TPU) Contention between TCNT Write and Increment Operations: If incrementing occurs in the T2 state of a TCNT write cycle, the TCNT write takes precedence and TCNT is not incremented. Figure 11.50 shows the timing in this case. TCNT write cycle T1 T2 φ TCNT address Address Write signal TCNT input clock TCNT N M TCNT write data Figure 11.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 11 16-Bit Timer Pulse Unit (TPU) Contention between TGR Write and Compare Match: If a compare match occurs in the T2 state of a TGR write cycle, the TGR write takes precedence and the compare match signal is inhibited. A compare match does not occur even if the same value as before is written. Figure 11.51 shows the timing in this case.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 11 16-Bit Timer Pulse Unit (TPU) Contention between Buffer Register Write and Compare Match: If a compare match occurs in the T2 state of a TGR write cycle, the data transferred to TGR by the buffer operation will be the data prior to the write. Figure 11.52 shows the timing in this case.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 11 16-Bit Timer Pulse Unit (TPU) Contention between TGR Read and Input Capture: If the input capture signal is generated in the T1 state of a TGR read cycle, the data that is read will be the data after input capture transfer. Figure 11.53 shows the timing in this case. TGR read cycle T1 T2 φ TGR address Address Read signal Input capture signal TGR X M M Internal data bus Figure 11.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 11 16-Bit Timer Pulse Unit (TPU) Contention between TGR Write and Input Capture: If the input capture signal is generated in the T2 state of a TGR write cycle, the input capture operation takes precedence and the write to TGR is not performed. Figure 11.54 shows the timing in this case. TGR write cycle T1 T2 φ TGR address Address Write signal Input capture signal TCNT TGR M M Figure 11.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 11 16-Bit Timer Pulse Unit (TPU) Contention between Buffer Register Write and Input Capture: If the input capture signal is generated in the T2 state of a buffer write cycle, the buffer operation takes precedence and the write to the buffer register is not performed. Figure 11.55 shows the timing in this case.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 11 16-Bit Timer Pulse Unit (TPU) Contention between Overflow/Underflow and Counter Clearing: If overflow/underflow and counter clearing occur simultaneously, the TCFV/TCFU flag in TSR is not set and TCNT clearing takes precedence. Figure 11.56 shows the operation timing when a TGR compare match is specified as the clearing source, and H'FFFF is set in TGR.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 11 16-Bit Timer Pulse Unit (TPU) Contention between TCNT Write and Overflow/Underflow: If there is an up-count or downcount in the T2 state of a TCNT write cycle, and overflow/underflow occurs, the TCNT write takes precedence and the TCFV/TCFU flag in TSR is not set. Figure 11.57 shows the operation timing when there is contention between TCNT write and overflow.
Section 11 16-Bit Timer Pulse Unit (TPU) Page 636 of 1434 H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 R01UH0166EJ0600 Rev. 6.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 12 Programmable Pulse Generator (PPG) (This function is not available in the H8S/2695) Section 12 Programmable Pulse Generator (PPG) (This function is not available in the H8S/2695) 12.1 Overview The H8S/2633 Group has a built-in programmable pulse generator (PPG) that provides pulse outputs by using the 16-bit timer-pulse unit (TPU) as a time base.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 12 Programmable Pulse Generator (PPG) (This function is not available in the H8S/2695) 12.1.2 Block Diagram Figure 12.1 shows a block diagram of the PPG.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 12.1.3 Section 12 Programmable Pulse Generator (PPG) (This function is not available in the H8S/2695) Pin Configuration Table 12.1 summarizes the PPG pins. Table 12.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 12 Programmable Pulse Generator (PPG) (This function is not available in the H8S/2695) 12.1.4 Registers Table 12.2 summarizes the PPG registers. Table 12.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 12 Programmable Pulse Generator (PPG) (This function is not available in the H8S/2695) 12.2 Register Descriptions 12.2.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 12 Programmable Pulse Generator (PPG) (This function is not available in the H8S/2695) NDERL Bits 7 to 0—Next Data Enable 7 to 0 (NDER7 to NDER0): These bits enable or disable pulse output on a bit-by-bit basis. However, the H8S/2633 Group has no output pins corresponding to NDRL.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 12.2.3 Section 12 Programmable Pulse Generator (PPG) (This function is not available in the H8S/2695) Next Data Registers H and L (NDRH, NDRL) NDRH and NDRL are 8-bit readable/writable registers that store the next data for pulse output. During pulse output, the contents of NDRH and NDRL are transferred to the corresponding bits in PODRH and PODRL when the TPU compare match event specified by PCR occurs.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 12 Programmable Pulse Generator (PPG) (This function is not available in the H8S/2695) Address H'FE2D Bit : Initial value : R/W : 7 6 5 4 3 2 1 0 NDR7 NDR6 NDR5 NDR4 NDR3 NDR2 NDR1 NDR0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 — — — — — — — — Address H'FE2F Bit : Initial value : 1 1 1 1 1 1 1 1 R/W — — — — — — — — : Different Triggers for
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 12 Programmable Pulse Generator (PPG) (This function is not available in the H8S/2695) Address H'FE2D Bit : 7 6 5 4 3 2 1 0 NDR7 NDR6 NDR5 NDR4 — — — — 0 0 0 0 1 1 1 1 R/W R/W R/W R/W — — — — 7 6 5 4 3 2 1 0 — — — — NDR3 NDR2 NDR1 NDR0 Initial value : R/W : Address H'FE2F Bit : Initial value : 1 1 1 1 0 0 0 0 R/W — — — — R/W R/W R/W R/W 4 3 2 1 0 12.2.
Section 12 Programmable Pulse Generator (PPG) (This function is not available in the H8S/2695) H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Bits 5 and 4—Group 2 Compare Match Select 1 and 0 (G2CMS1, G2CMS0): These bits select the compare match that triggers pulse output group 2 (pins PO11 to PO8).
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 12.2.6 Section 12 Programmable Pulse Generator (PPG) (This function is not available in the H8S/2695) PPG Output Mode Register (PMR) Bit : Initial value : R/W : 7 6 5 4 3 2 1 0 G3INV G2INV G1INV G0INV G3NOV G2NOV G1NOV G0NOV 1 1 1 1 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W PMR is an 8-bit readable/writable register that selects pulse output inversion and non-overlapping operation for each group.
Section 12 Programmable Pulse Generator (PPG) (This function is not available in the H8S/2695) H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Bit 5—Group 1 Inversion (G1INV): Selects direct output or inverted output for pulse output group 1 (pins PO7 to PO4). However, the H8S/2633 Group has no pins corresponding to pulse output group 1.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 12 Programmable Pulse Generator (PPG) (This function is not available in the H8S/2695) Bit 2—Group 2 Non-Overlap (G2NOV): Selects normal or non-overlapping operation for pulse output group 2 (pins PO11 to PO8).
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 12 Programmable Pulse Generator (PPG) (This function is not available in the H8S/2695) 12.2.7 Port 1 Data Direction Register (P1DDR) Bit : 7 6 5 4 3 2 1 0 P17DDR P16DDR P15DDR P14DDR P13DDR P12DDR P11DDR P10DDR Initial value : 0 0 0 0 0 0 0 0 R/W W W W W W W W W : P1DDR is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port 1.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 12.3 Operation 12.3.1 Overview Section 12 Programmable Pulse Generator (PPG) (This function is not available in the H8S/2695) PPG pulse output is enabled when the corresponding bits in P1DDR and NDER are set to 1. In this state the corresponding PODR contents are output. When the compare match event specified by PCR occurs, the corresponding NDR bit contents are transferred to PODR to update the output values. Figure 12.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 12 Programmable Pulse Generator (PPG) (This function is not available in the H8S/2695) 12.3.2 Output Timing If pulse output is enabled, NDR contents are transferred to PODR and output when the specified compare match event occurs. Figure 12.3 shows the timing of these operations for the case of normal output in groups 2 and 3, triggered by compare match A.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 12.3.3 Section 12 Programmable Pulse Generator (PPG) (This function is not available in the H8S/2695) Normal Pulse Output Sample Setup Procedure for Normal Pulse Output: Figure 12.4 shows a sample procedure for setting up normal pulse output.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 12 Programmable Pulse Generator (PPG) (This function is not available in the H8S/2695) Example of Normal Pulse Output (Example of Five-Phase Pulse Output): Figure 12.5 shows an example in which pulse output is used for cyclic five-phase pulse output.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 12.3.4 Section 12 Programmable Pulse Generator (PPG) (This function is not available in the H8S/2695) Non-Overlapping Pulse Output Sample Setup Procedure for Non-Overlapping Pulse Output: Figure 12.6 shows a sample procedure for setting up non-overlapping pulse output. [1] Set TIOR to make TGRA and TGRB an output compare registers (with output disabled).
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 12 Programmable Pulse Generator (PPG) (This function is not available in the H8S/2695) Example of Non-Overlapping Pulse Output (Example of Four-Phase Complementary NonOverlapping Output): Figure 12.7 shows an example in which pulse output is used for fourphase complementary non-overlapping pulse output.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 12 Programmable Pulse Generator (PPG) (This function is not available in the H8S/2695) [1] Set up the TPU channel to be used as the output trigger channel so that TGRA and TGRB are output compare registers. Set the trigger period in TGRB and the non-overlap margin in TGRA, and set the counter to be cleared by compare match B. Set the TGIEA bit in TIER to 1 to enable the TGIA interrupt.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 12 Programmable Pulse Generator (PPG) (This function is not available in the H8S/2695) 12.3.5 Inverted Pulse Output If the G3INV, G2INV, G1INV, and G0INV bits in PMR are cleared to 0, values that are the inverse of the PODR contents can be output. Figure 12.8 shows the outputs when G3INV and G2INV are cleared to 0, in addition to the settings of figure 12.7.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 12.3.6 Section 12 Programmable Pulse Generator (PPG) (This function is not available in the H8S/2695) Pulse Output Triggered by Input Capture Pulse output can be triggered by TPU input capture as well as by compare match. If TGRA functions as an input capture register in the TPU channel selected by PCR, pulse output will be triggered by the input capture signal. Figure 12.9 shows the timing of this output.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 12 Programmable Pulse Generator (PPG) (This function is not available in the H8S/2695) Figure 12.10 illustrates the non-overlapping pulse output operation. DDR NDER Q Compare match A Compare match B C Q PODR D Pulse output pin Q NDR D Internal data bus Normal output/inverted output Figure 12.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 13 8-Bit Timers (TMR) (This function is not available in the H8S/2695) Section 13 8-Bit Timers (TMR) (This function is not available in the H8S/2695) 13.1 Overview The H8S/2633 Group includes an 8-bit timer module with four channels (TMR0, TMR1, TMR2, and TMR3).
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 13 8-Bit Timers (TMR) (This function is not available in the H8S/2695) 13.1.2 Block Diagram Figure 13.1 shows a block diagram of the 8-bit timer module (TMR0, TMR1).
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 13.1.3 Section 13 8-Bit Timers (TMR) (This function is not available in the H8S/2695) Pin Configuration Table 13.1 summarizes the input and output pins of the 8-bit timer. Table 13.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 13 8-Bit Timers (TMR) (This function is not available in the H8S/2695) 13.1.4 Register Configuration Table 13.2 summarizes the registers of the 8-bit timer module. Table 13.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 13 8-Bit Timers (TMR) (This function is not available in the H8S/2695) 13.2 Register Descriptions 13.2.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 13 8-Bit Timers (TMR) (This function is not available in the H8S/2695) The timer output can be freely controlled by these compare match signals and the settings of bits OS1 and OS0 of TCSR. TCORA0 and TCORA1 are each initialized to H'FF by a reset and in hardware standby mode. 13.2.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 13 8-Bit Timers (TMR) (This function is not available in the H8S/2695) Bit 7—Compare Match Interrupt Enable B (CMIEB): Selects whether CMFB interrupt requests (CMIB) are enabled or disabled when the CMFB flag of TCSR is set to 1.
Section 13 8-Bit Timers (TMR) (This function is not available in the H8S/2695) H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Bits 2 to 0—Clock Select 2 to 0 (CKS2 to CKS0): These bits select whether the clock input to TCNT is an internal or external clock. Three internal clocks can be selected, all divided from the system clock (φ): φ/8, φ/64, and φ/8192. The falling edge of the selected internal clock triggers the count.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 13.2.
Section 13 8-Bit Timers (TMR) (This function is not available in the H8S/2695) H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Bit 7—Compare Match Flag B (CMFB): Status flag indicating whether the values of TCNT and TCORB match.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 13 8-Bit Timers (TMR) (This function is not available in the H8S/2695) Bit 4 ADTE Description 0 A/D converter start requests by compare match A are disabled 1 A/D converter start requests by compare match A are enabled (Initial value) Bits 3 to 0—Output Select 3 to 0 (OS3 to OS0): These bits specify how the timer output level is to be changed by a compare match of TCOR and TCNT.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 13 8-Bit Timers (TMR) (This function is not available in the H8S/2695) 13.2.6 Bit Module Stop Control Register A (MSTPCRA) : 7 6 5 4 3 2 1 0 MSTPA7 MSTPA6 MSTPA5 MSTPA4 MSTPA3 MSTPA2 MSTPA1 MSTPA0 Initial value : R/W : 0 0 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W MSTPCRA is an 8-bit readable/writable register that performs module stop mode control.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 13.3 Operation 13.3.1 TCNT Incrementation Timing Section 13 8-Bit Timers (TMR) (This function is not available in the H8S/2695) TCNT is incremented by input clock pulses (either internal or external). Internal Clock: Three different internal clock signals (φ/8, φ/64, or φ/8192) divided from the system clock (φ) can be selected, by setting bits CKS2 to CKS0 in TCR. Figure 13.2 shows the count timing.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 13 8-Bit Timers (TMR) (This function is not available in the H8S/2695) φ External clock input Clock input to TCNT TCNT N–1 N N+1 Figure 13.3 Count Timing for External Clock Input 13.3.2 Compare Match Timing Setting of Compare Match Flags A and B (CMFA, CMFB): The CMFA and CMFB flags in TCSR are set to 1 by a compare match signal generated when the TCOR and TCNT values match.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 13 8-Bit Timers (TMR) (This function is not available in the H8S/2695) Timer Output Timing: When compare match A or B occurs, the timer output changes a specified by bits OS3 to OS0 in TCSR. Depending on these bits, the output can remain the same, change to 0, change to 1, or toggle. Figure 13.5 shows the timing when the output is set to toggle at compare match A. φ Compare match A signal Timer output pin Figure 13.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 13 8-Bit Timers (TMR) (This function is not available in the H8S/2695) 13.3.3 Timing of External RESET on TCNT TCNT is cleared at the rising edge of an external reset input, depending on the settings of the CCLR1 and CCLR0 bits in TCR. The clear pulse width must be at least 1.5 states. Figure 13.7 shows the timing of this operation. φ External reset input pin Clear signal TCNT N–1 N H'00 Figure 13.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 13.3.5 Section 13 8-Bit Timers (TMR) (This function is not available in the H8S/2695) Operation with Cascaded Connection If bits CKS2 to CKS0 in either TCR0 or TCR1 are set to B'100, the 8-bit timers of the two channels are cascaded.
Section 13 8-Bit Timers (TMR) (This function is not available in the H8S/2695) 13.4 Interrupts 13.4.1 Interrupt Sources and DTC Activation H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 (The H8S/2695 does not have a DTC function or an 8-bit timer) There are three 8-bit timer interrupt sources: CMIA, CMIB, and OVI. Their relative priorities are shown in table 13.3.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 13.5 Section 13 8-Bit Timers (TMR) (This function is not available in the H8S/2695) Sample Application In the example below, the 8-bit timer is used to generate a pulse output with a selected duty cycle, as shown in figure 13.9. The control bits are set as follows: [1] In TCR, bit CCLR1 is cleared to 0 and bit CCLR0 is set to 1 so that TCNT is cleared by comparing and matching TCORA.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 13 8-Bit Timers (TMR) (This function is not available in the H8S/2695) 13.6 Usage Notes Application programmers should note that the following kinds of contention can occur in the 8-bit timer. 13.6.1 Contention between TCNT Write and Clear If a timer counter clock pulse is generated during the T2 state of a TCNT write cycle, the clear takes priority, so that the counter is cleared and the write is not performed. Figure 13.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 13.6.2 Section 13 8-Bit Timers (TMR) (This function is not available in the H8S/2695) Contention between TCNT Write and Increment If a timer counter clock pulse is generated during the T2 state of a TCNT write cycle, the write takes priority and the counter is not incremented. Figure 13.11 shows this operation.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 13 8-Bit Timers (TMR) (This function is not available in the H8S/2695) 13.6.3 Contention between TCOR Write and Compare Match During the T2 state of a TCOR write cycle, the TCOR write has priority and the compare match signal is disabled even if a compare match event occurs. Figure 13.12 shows this operation.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 13.6.4 Section 13 8-Bit Timers (TMR) (This function is not available in the H8S/2695) Contention between Compare Matches A and B If compare match events A and B occur at the same time, the 8-bit timer operates in accordance with the priorities for the output statuses set for compare match A and compare match B, as shown in table 13.4. Table 13.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 13 8-Bit Timers (TMR) (This function is not available in the H8S/2695) Table 13.5 Switching of Internal Clock and TCNT Operation No.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 No. 4 Section 13 8-Bit Timers (TMR) (This function is not available in the H8S/2695) Timing of Switchover by Means of CKS1 and CKS0 Bits TCNT Clock Operation Switching from high to high Clock before switchover Clock after switchover TCNT clock TCNT N N+1 N+2 CKS bit write Notes: 1. 2. 3. 4. 13.6.6 Includes switching from low to stop, and from stop to low. Includes switching from stop to high.
Section 13 8-Bit Timers (TMR) (This function is not available in the H8S/2695) Page 686 of 1434 H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 R01UH0166EJ0600 Rev. 6.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 14 14-Bit PWM D/A (This function is not available in the H8S/2695) Section 14 14-Bit PWM D/A (This function is not available in the H8S/2695) 14.1 Overview The H8S/2633 Group has an on-chip 14-bit pulse-width modulator (PWM) with four output channels. Each channel can be connected to an external low-pass filter to operate as a 14-bit D/A converter. Both channels share the same counter (DACNT) and control register (DACR). 14.1.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 14 14-Bit PWM D/A (This function is not available in the H8S/2695) 14.1.2 Block Diagram Figure 14.1 shows a block diagram of the PWM D/A module.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 14.1.3 Section 14 14-Bit PWM D/A (This function is not available in the H8S/2695) Pin Configuration Table 14.1 lists the pins used by the PWM D/A module. Table 14.1 Input and Output Pins Name Abbr.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 14 14-Bit PWM D/A (This function is not available in the H8S/2695) 14.2 Register Descriptions 14.2.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 14.2.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 14 14-Bit PWM D/A (This function is not available in the H8S/2695) Bit 1—Carrier Frequency Select (CFS) Bit 1 CFS Description 0 Base cycle = resolution (T) × 64 DADR range = H'0401 to H'FFFD 1 Base cycle = resolution (T) × 256 DADR range = H'0103 to H'FFFF (Initial value) Bit 0—Reserved: This bit cannot be modified and is always read as 1.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 14 14-Bit PWM D/A (This function is not available in the H8S/2695) Bit 7—Test Mode (TEST): Selects test mode, which is used in testing the chip. Normally this bit should be cleared to 0. Bit 7 TEST Description 0 PWM (D/A) in user state: normal operation 1 PWM (D/A) in test state: correct conversion results unobtainable (Initial value) Bit 6—PWM Enable (PWME): Starts or stops the PWM D/A counter (DACNT).
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 14 14-Bit PWM D/A (This function is not available in the H8S/2695) Bit 1—Output Select (OS): Selects the phase of the PWM D/A output. Bit 1 OS Description 0 Direct PWM output 1 Inverted PWM output (Initial value) Bit 0—Clock Select (CKS): Selects the PWM D/A resolution. If the system clock (φ) frequency is 10 MHz, resolutions of 100 ns and 200 ns can be selected.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 14 14-Bit PWM D/A (This function is not available in the H8S/2695) Bit 2—Module Stop (MSTPB2): Specifies PWM0 module stop mode. Bit 2 MSTPB2 Description 0 PWM0 module stop mode is cleared 1 PWM0 module stop mode is set (Initial value) Bit 1—Module Stop (MSTPB1): Specifies PWM1 module stop mode. Bit 1 MSTPB1 Description 0 PWM1 module stop mode is cleared 1 PWM1 module stop mode is set 14.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 14 14-Bit PWM D/A (This function is not available in the H8S/2695) Example 1: Write to DACNT MOV.W R0, @DACNT ; Write R0 contents to DACNT Example 2: Read DADRA MOV.W @DADRA, R0 ; Copy contents of DADRA to R0 Table 14.3 Read and Write Access Methods for 16-Bit Registers Read Write Register Name Word Byte Word Byte DADRA and DADRB Yes Yes Yes × DACNT Yes × Yes × Notes: Yes: Permitted type of access.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 14 14-Bit PWM D/A (This function is not available in the H8S/2695) Upper-Byte Write CPU (H'AA) Upper byte Module data bus Bus interface TEMP (H'AA) DACNTH ( ) DACNTL ( ) Lower-Byte Write CPU (H'57) Lower byte Module data bus Bus interface TEMP (H'AA) DACNTH (H'AA) DACNTL (H'57) Figure 14.2 (a) Access to DACNT (CPU Writes H'AA57 to DACNT) R01UH0166EJ0600 Rev. 6.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 14 14-Bit PWM D/A (This function is not available in the H8S/2695) Upper-Byte Read CPU (H'AA) Upper byte Module data bus Bus interface TEMP (H'57) DACNTH (H'AA) DACNTL (H'57) Lower-Byte Read CPU (H'57) Lower byte Module data bus Bus interface TEMP (H'57) DACNTH ( ) DACNTL ( ) Figure 14.2 (b) Access to DACNT (CPU Reads H'AA57 from DACNT) Page 698 of 1434 R01UH0166EJ0600 Rev. 6.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 14.4 Section 14 14-Bit PWM D/A (This function is not available in the H8S/2695) Operation A PWM waveform like the one shown in figure 14.3 is output from the PWMX pin. When OS = 0, the value in DADR corresponds to the total width (TL) of the low (0) pulses output in one conversion cycle (256 pulses when CFS = 0, 64 pulses when CFS = 1).
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 14 14-Bit PWM D/A (This function is not available in the H8S/2695) Table 14.4 Settings and Operation (Examples when φ = 10 MHz) Fixed DADR Bits Resolution Base Conversion TL (if OS = 0) CKS T (µs) CFS Cycle (µs) Cycle (µs) TH (if OS = 1) 0 0.1 0 6.4 1638.4 1. Always low (or high) (DADR = H'0001 to H'03FD) 2. (Data value) × T (DADR = H'0401 to H'FFFD) 1 25.6 1638.4 1. Always low (or high) (DADR = H'0003 to H'00FF) 2.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 14 14-Bit PWM D/A (This function is not available in the H8S/2695) 1. OS = 0 (DADR corresponds to TL) a. CFS = 0 [base cycle = resolution (T) × 64] 1 conversion cycle tf1 tL1 tf2 tf255 tL2 tL3 tL255 tf256 tL256 tf1 = tf2 = tf3 = · · · = tf255 = tf256 = T × 64 tL1 + tL2 + tL3 + · · · + tL255 + tL256 = TL Figure 14.4 (1) Output Waveform b.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 14 14-Bit PWM D/A (This function is not available in the H8S/2695) 2. OS = 1 (DADR corresponds to TH) a. CFS = 0 [base cycle = resolution (T) × 64] 1 conversion cycle tf1 tH1 tf2 tf255 tH2 tH3 tH255 tf256 tH256 tf1 = tf2 = tf3 = · · · = tf255 = tf256 = T × 64 tH1 + tH2 + tH3 + · · · + tH255 + tH256 = TH Figure 14.4 (3) Output Waveform b.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 15 Watchdog Timer (WDT1 is not available in the H8S/2695) Section 15 Watchdog Timer (WDT1 is not available in the H8S/2695) 15.1 Overview The H8S/2633 Group has a two channel inbuilt watchdog timer, (WDT0/WDT1). The WDT outputs an overflow signal (WDTOVF) if a system crash prevents the CPU from writing to the timer counter, allowing it to overflow.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 15 Watchdog Timer (WDT1 is not available in the H8S/2695) 15.1.2 Block Diagram Figure 15.1 (a) and 15.1 (b) show a block diagram of the WDT.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Internal NMI Interrupt request signal Interrupt control Overflow Clock Clock select Reset control Internal reset signal* φ/2 φ/64 φ/128 φ/512 φ/2048 φ/8192 φ/32768 φ/131072 Internal clock BUZZ TCNT TCSR Module bus Bus interface φSUB/2 φSUB/4 φSUB/8 φSUB/16 φSUB/32 φSUB/64 φSUB/128 φSUB/256 Internal bus WOVI1 (Interrupt request signal) Section 15 Watchdog Timer (WDT1 is not available in the H8S/2695) WDT Legend: TCSR: Timer
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 15 Watchdog Timer (WDT1 is not available in the H8S/2695) 15.1.3 Pin Configuration Table 15.1 describes the WDT output pin. Table 15.1 WDT Pin Name Symbol I/O Function Watchdog timer overflow WDTOVF Output Outputs counter overflow signal in watchdog timer mode Buzzer output BUZZ* Output Outputs clock selected by watchdog timer (WDT1) Note: * This function is not available in the H8S/2695. 15.1.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 15 Watchdog Timer (WDT1 is not available in the H8S/2695) 15.2 Register Descriptions 15.2.1 Timer Counter (TCNT) Bit : Initial value : R/W : 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W TCNT is an 8-bit readable/writable* up-counter. When the TME bit is set to 1 in TCSR, TCNT starts counting pulses generated from the internal clock source selected by bits CKS2 to CKS0 in TCSR.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 15 Watchdog Timer (WDT1 is not available in the H8S/2695) 15.2.2 Timer Control/Status Register (TCSR) TCSR0 Bit : Initial value : R/W : 7 6 5 4 3 2 1 0 OVF WT/IT TME — — CKS2 CKS1 CKS0 0 0 0 1 1 0 0 0 R/(W)* R/W R/W — — R/W R/W R/W Note: * Only a 0 can be written, for flag clearing.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 15 Watchdog Timer (WDT1 is not available in the H8S/2695) Bit 7—Overflow Flag (OVF): Indicates that TCNT has overflowed from H'FF to H'00.
Section 15 Watchdog Timer (WDT1 is not available in the H8S/2695) H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 WDT1* Mode Select WDT1 WT/IT Description 0 Interval timer mode: WDT1 requests an interval timer interrupt (WOVI) from the CPU when the TCNT overflows. 1 Watchdog timer mode: WDT1 requests a reset or an NMI interrupt from the CPU when the TCNT overflows. (Initial value) Note: * In the case of the H8S/2695, only 0 should be written to the WT/IT bit in the TCSR1 register.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 15 Watchdog Timer (WDT1 is not available in the H8S/2695) WDT0 TCSR Bit 3—Reserved Bit: This bit is always read as 1 and cannot be modified. WDT1 TCSR Bit 3—Reset or NMI (RST/NMI): This bit is used to choose between an internal reset request and an NMI request when the TCNT overflows during the watchdog timer mode. Bit 3 RTS/NMI Description 0 NMI request. 1 Internal reset request.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 15 Watchdog Timer (WDT1 is not available in the H8S/2695) WDT1* Input Clock Select 1 Description Bit 4 PSS Bit 2 CKS2 Bit 1 CKS1 Bit 0 CKS0 Clock Overflow Period* (where φ = 25 MHz) (where φ SUB = 32.768 kHz) 0 0 0 0 φ/2 (Initial value) 20.4 µs 1 φ/64 655.3 µs 0 φ/128 1.3 ms 1 φ/512 5.2 ms 0 φ/2048 20.9 ms 1 φ/8192 83.8 ms 0 φ/32768 335.5 ms 1 φ/131072 1.34 s 0 φSUB/2 15.6 ms 1 φSUB/4 31.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 15.2.3 Section 15 Watchdog Timer (WDT1 is not available in the H8S/2695) Reset Control/Status Register (RSTCSR) Bit : Initial value : R/W : 7 6 5 4 3 2 1 0 WOVF RSTE RSTS — — — — — 0 0 0 1 1 1 1 1 R/(W)* R/W R/W — — — — — Note: * Only 0 can be written, for flag clearing.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 15 Watchdog Timer (WDT1 is not available in the H8S/2695) Bit 5—Reset Select (RSTS): Selects the type of internal reset generated if TCNT overflows during watchdog timer operation. For details of the types of reset, see section 4, Exception Handling. Bit 5 RSTS Description 0 Power-on reset 1 Manual reset (Initial value) Bits 4 to 0—Reserved: These bits are always read as 1 and cannot be modified. 15.2.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 15.2.5 Section 15 Watchdog Timer (WDT1 is not available in the H8S/2695) Notes on Register Access The watchdog timer’s TCNT, TCSR, and RSTCSR registers differ from other registers in being more difficult to write to. The procedures for writing to and reading these registers are given below. Writing to TCNT and TCSR: These registers must be written to by a word transfer instruction. They cannot be written to with byte instructions.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 15 Watchdog Timer (WDT1 is not available in the H8S/2695) Writing to RSTCSR: RSTCSR must be written to by word transfer instruction to address H'FF76. It cannot be written to with byte instructions. Figure 15.3 shows the format of data written to RSTCSR. The method of writing 0 to the WOVF bit differs from that for writing to the RSTE and RSTS bits.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 15.3 Operation 15.3.1 Watchdog Timer Operation Section 15 Watchdog Timer (WDT1 is not available in the H8S/2695) To use the WDT as a watchdog timer, set the WT/IT bit in TCSR and TME bit to 1. Software must prevent TCNT overflows by rewriting the TCNT value (normally be writing H'00) before overflows occurs. This ensures that TCNT does not overflow while the system is operating normally.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 15 Watchdog Timer (WDT1 is not available in the H8S/2695) TCNT count Overflow H'FF Time H'00 WT/IT=1 TME=1 H'00 written to TCNT WT/IT=1 TME=1 WOVF=1 WDTOVF and internal reset are generated H'00 written to TCNT WDTOVF signal 132 states*2 Internal reset signal*1 518 states Legend: WT/IT: Timer mode select bit TME: Timer enable bit Notes: 1. The internal reset signal is generated only if the RSTE bit is set to 1. 2.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 15.3.2 Section 15 Watchdog Timer (WDT1 is not available in the H8S/2695) Interval Timer Operation To use the WDT as an interval timer, clear the WT/IT bit in TCSR to 0 and set the TME bit to 1. An interval timer interrupt (WOVI) is generated each time TCNT overflows, provided that the WDT is operating as an interval timer, as shown in figure 15.5. This function can be used to generate interrupt requests at regular intervals.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 15 Watchdog Timer (WDT1 is not available in the H8S/2695) φ TCNT H'FF H'00 Overflow signal (internal signal) OVF Figure 15.6 Timing of Setting of OVF 15.3.4 Timing of Setting of Watchdog Timer Overflow Flag (WOVF) In the WDT0, the WOVF flag is set to 1 if TCNT overflows during watchdog timer operation. At the same time, the WDTOVF signal goes low.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 15.4 Section 15 Watchdog Timer (WDT1 is not available in the H8S/2695) Interrupts During interval timer mode operation, an overflow generates an interval timer interrupt (WOVI). The interval timer interrupt is requested whenever the OVF flag is set to 1 in TCSR. OVF must be cleared to 0 in the interrupt handling routine.
Section 15 Watchdog Timer (WDT1 is not available in the H8S/2695) 15.5.2 H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Changing Value of PSS and CKS2 to CKS0 If bits PSS and CKS2 to CKS0 in TCSR are written to while the WDT is operating, errors could occur in the incrementation. Software must stop the watchdog timer (by clearing the TME bit to 0) before changing the value of bits PSS and CKS2 to CKS0. 15.5.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 15.5.6 Section 15 Watchdog Timer (WDT1 is not available in the H8S/2695) OVF Flag Clearing in Interval Timer Mode When the OVF Flag setting conflicts with the OVF flag reading in interval timer mode, writing 0 to the OVF bit may not clear the flag even though the OVF bit has been read while it is 1.
Section 15 Watchdog Timer (WDT1 is not available in the H8S/2695) Page 724 of 1434 H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 R01UH0166EJ0600 Rev. 6.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 16 Serial Communication Interface (SCI, IrDA) (The H8S/2695 is not equipped with an IrDA function) Section 16 Serial Communication Interface (SCI, IrDA) (The H8S/2695 is not equipped with an IrDA function) 16.1 Overview The H8S/2633 is equipped with 5 independent serial communication interface (SCI) channels. The SCI can handle both asynchronous and clocked synchronous serial communication.
Section 16 Serial Communication Interface (SCI, IrDA) (The H8S/2695 is not equipped with an IrDA function) H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Clocked Synchronous mode ⎯ Serial data communication synchronized with a clock Serial data communication can be carried out with other chips that have a synchronous communication function ⎯ One serial data transfer format Data length: 8 bits ⎯ Receive error detection: Overrun errors detected • Full-duplex communication capability ⎯
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 16.1.2 Section 16 Serial Communication Interface (SCI, IrDA) (The H8S/2695 is not equipped with an IrDA function) Block Diagram Bus interface Figure 16.1 shows a block diagram of the SCI.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 16 Serial Communication Interface (SCI, IrDA) (The H8S/2695 is not equipped with an IrDA function) 16.1.3 Pin Configuration Table 16.1 shows the serial pins for each SCI channel. Table 16.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 16.1.4 Section 16 Serial Communication Interface (SCI, IrDA) (The H8S/2695 is not equipped with an IrDA function) Register Configuration The SCI has the internal registers shown in table 16.2. These registers are used to specify asynchronous mode or clocked synchronous mode, the data format , and the bit rate, and to control transmitter/receiver. Table 16.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 16 Serial Communication Interface (SCI, IrDA) (The H8S/2695 is not equipped with an IrDA function) Channel Name Abbreviation R/W Initial Value Address* 3 Serial mode register 3 SMR3 R/W H'00 H'FDD0 Bit rate register 3 BRR3 R/W H'FF H'FDD1 Serial control register 3 SCR3 R/W H'00 H'FDD2 Transmit data register 3 TDR3 R/W H'FF H'FDD3 Serial status register 3 SSR3 2 R/(W)* H'84 H'FDD4 Receive data regist
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 16 Serial Communication Interface (SCI, IrDA) (The H8S/2695 is not equipped with an IrDA function) 16.2 Register Descriptions 16.2.1 Receive Shift Register (RSR) Bit : 7 6 5 4 3 2 1 0 R/W : — — — — — — — — RSR is a register used to receive serial data. The SCI sets serial data input from the RxD pin in RSR in the order received, starting with the LSB (bit 0), and converts it to parallel data.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 16 Serial Communication Interface (SCI, IrDA) (The H8S/2695 is not equipped with an IrDA function) 16.2.3 Transmit Shift Register (TSR) Bit : 7 6 5 4 3 2 1 0 R/W : — — — — — — — — TSR is a register used to transmit serial data. To perform serial data transmission, the SCI first transfers transmit data from TDR to TSR, then sends the data to the TxD pin starting with the LSB (bit 0).
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 16.2.5 Section 16 Serial Communication Interface (SCI, IrDA) (The H8S/2695 is not equipped with an IrDA function) Serial Mode Register (SMR) Bit 7 6 5 4 3 2 1 0 C/A CHR PE O/E STOP MP CKS1 CKS0 : 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Initial value : R/W : SMR is an 8-bit register used to set the SCI’s serial transfer format and select the baud rate generator clock source.
Section 16 Serial Communication Interface (SCI, IrDA) (The H8S/2695 is not equipped with an IrDA function) H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Bit 5—Parity Enable (PE): In asynchronous mode, selects whether or not parity bit addition is performed in transmission, and parity bit checking in reception. In clocked synchronous mode with a multiprocessor format, parity bit addition and checking is not performed, regardless of the PE bit setting.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 16 Serial Communication Interface (SCI, IrDA) (The H8S/2695 is not equipped with an IrDA function) Bit 3—Stop Bit Length (STOP): Selects 1 or 2 bits as the stop bit length in asynchronous mode. The STOP bits setting is only valid in asynchronous mode. If clocked synchronous mode is set the STOP bit setting is invalid since stop bits are not added.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 16 Serial Communication Interface (SCI, IrDA) (The H8S/2695 is not equipped with an IrDA function) Bits 1 and 0—Clock Select 1 and 0 (CKS1, CKS0): These bits select the clock source for the baud rate generator. The clock source can be selected from φ, φ/4, φ/16, and φ/64, according to the setting of bits CKS1 and CKS0. For the relation between the clock source, the bit rate register setting, and the baud rate, see section 16.2.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 16 Serial Communication Interface (SCI, IrDA) (The H8S/2695 is not equipped with an IrDA function) Bit 6—Receive Interrupt Enable (RIE): Enables or disables receive data full interrupt (RXI) request and receive error interrupt (ERI) request generation when serial receive data is transferred from RSR to RDR and the RDRF flag in SSR is set to 1.
Section 16 Serial Communication Interface (SCI, IrDA) (The H8S/2695 is not equipped with an IrDA function) H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Bit 3—Multiprocessor Interrupt Enable (MPIE): Enables or disables multiprocessor interrupts. The MPIE bit setting is only valid in asynchronous mode when the MP bit in SMR is set to 1. The MPIE bit setting is invalid in clocked synchronous mode or when the MP bit is cleared to 0.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 16 Serial Communication Interface (SCI, IrDA) (The H8S/2695 is not equipped with an IrDA function) Bits 1 and 0—Clock Enable 1 and 0 (CKE1, CKE0): These bits are used to select the SCI clock source and enable or disable clock output from the SCK pin. The combination of the CKE1 and CKE0 bits determines whether the SCK pin functions as an I/O port, the serial clock output pin, or the serial clock input pin.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 16 Serial Communication Interface (SCI, IrDA) (The H8S/2695 is not equipped with an IrDA function) 16.2.7 Serial Status Register (SSR) Bit : Initial value : R/W : 7 6 5 4 3 2 1 0 TDRE RDRF ORER FER PER TEND MPB MPBT 1 0 0 0 0 1 0 0 R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R R R/W Note: * Only 0 can be written, to clear the flag.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 16 Serial Communication Interface (SCI, IrDA) (The H8S/2695 is not equipped with an IrDA function) Bit 6—Receive Data Register Full (RDRF): Indicates that the received data is stored in RDR.
Section 16 Serial Communication Interface (SCI, IrDA) (The H8S/2695 is not equipped with an IrDA function) H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Bit 4—Framing Error (FER): Indicates that a framing error occurred during reception in asynchronous mode, causing abnormal termination.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 16 Serial Communication Interface (SCI, IrDA) (The H8S/2695 is not equipped with an IrDA function) Bit 2—Transmit End (TEND): Indicates that there is no valid data in TDR when the last bit of the transmit character is sent, and transmission has been ended. The TEND flag is read-only and cannot be modified.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 16 Serial Communication Interface (SCI, IrDA) (The H8S/2695 is not equipped with an IrDA function) Bit 0—Multiprocessor Bit Transfer (MPBT): When transmission is performed using multiprocessor format in asynchronous mode, MPBT stores the multiprocessor bit to be added to the transmit data. The MPBT bit setting is invalid when multiprocessor format is not used, when not transmitting, and in clocked synchronous mode.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 16 Serial Communication Interface (SCI, IrDA) (The H8S/2695 is not equipped with an IrDA function) Table 16.3 BRR Settings for Various Bit Rates (Asynchronous Mode) φ = 2 MHz φ = 2.097152 MHz φ = 2.4576 MHz Bit Rate (bit/s) n N Error (%) n N Error (%) N Error (%) 110 1 141 0.03 1 148 –0.04 1 174 150 1 103 0.16 1 108 0.21 1 300 0 207 0.16 0 217 0.21 600 0 103 0.16 0 108 0.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 16 Serial Communication Interface (SCI, IrDA) (The H8S/2695 is not equipped with an IrDA function) φ = 6 MHz Bit Rate (bit/s) n N Error (%) 110 2 106 150 2 300 φ = 6.144 MHz φ = 7.3728 MHz φ = 8 MHz N Error (%) n N Error (%) N Error (%) –0.44 2 108 0.08 2 130 –0.07 2 141 0.03 77 0.16 2 79 0.00 2 95 0.00 2 103 0.16 1 155 0.16 1 159 0.00 1 191 0.00 1 207 0.16 600 1 77 0.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 16 Serial Communication Interface (SCI, IrDA) (The H8S/2695 is not equipped with an IrDA function) φ = 14 MHz φ = 14.7456 MHz Bit Rate (bit/s) n N Error (%) 110 2 248 150 2 300 φ = 16 MHz φ = 17.2032 MHz N Error (%) n N Error (%) n N Error (%) –0.17 3 64 0.70 3 70 0.03 3 75 0.48 181 0.16 2 191 0.00 2 207 0.16 2 223 0.00 2 90 0.16 2 95 0.00 2 103 0.16 2 111 0.00 600 1 181 0.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 16 Serial Communication Interface (SCI, IrDA) (The H8S/2695 is not equipped with an IrDA function) Table 16.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 16 Serial Communication Interface (SCI, IrDA) (The H8S/2695 is not equipped with an IrDA function) The BRR setting is found from the following formulas.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 16 Serial Communication Interface (SCI, IrDA) (The H8S/2695 is not equipped with an IrDA function) Table 16.5 shows the maximum bit rate for each frequency in asynchronous mode. Tables 16.6 and 16.7 show the maximum bit rates with external clock input. Table 16.5 Maximum Bit Rate for Each Frequency (Asynchronous Mode) φ (MHz) Maximum Bit Rate (bit/s) n N 2 62500 0 0 2.097152 65536 0 0 2.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 16 Serial Communication Interface (SCI, IrDA) (The H8S/2695 is not equipped with an IrDA function) Table 16.6 Maximum Bit Rate with External Clock Input (Asynchronous Mode) φ (MHz) External Input Clock (MHz) Maximum Bit Rate (bit/s) 2 0.5000 31250 2.097152 0.5243 32768 2.4576 0.6144 38400 3 0.7500 46875 3.6864 0.9216 57600 4 1.0000 62500 4.9152 1.2288 76800 5 1.2500 78125 6 1.5000 93750 6.144 1.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 16 Serial Communication Interface (SCI, IrDA) (The H8S/2695 is not equipped with an IrDA function) Table 16.7 Maximum Bit Rate with External Clock Input (Clocked Synchronous Mode) φ (MHz) External Input Clock (MHz) Maximum Bit Rate (bit/s) 2 0.3333 333333.3 4 0.6667 666666.7 6 1.0000 1000000.0 8 1.3333 1333333.3 10 1.6667 1666666.7 12 2.0000 2000000.0 14 2.3333 2333333.3 16 2.6667 2666666.7 18 3.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 16 Serial Communication Interface (SCI, IrDA) (The H8S/2695 is not equipped with an IrDA function) Bit 3—Smart Card Data Transfer Direction (SDIR): Selects the serial/parallel conversion format. This bit is valid when 8-bit data is used as the transmit/receive format.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 16 Serial Communication Interface (SCI, IrDA) (The H8S/2695 is not equipped with an IrDA function) 16.2.10 IrDA Control Register (IrCR) Bit : Initial value : R/W : 7 6 5 4 3 2 1 0 IrE IrCKS2 IrCKS1 IrCKS0 — — — — 0 0 0 0 0 0 0 0 R/W R/W R/W R/W — — — — IrCR is an 8-bit read/write register that selects the SCI0 function. IrCR is initialized to H'00 when in hardware standby mode.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 16 Serial Communication Interface (SCI, IrDA) (The H8S/2695 is not equipped with an IrDA function) 16.2.
Section 16 Serial Communication Interface (SCI, IrDA) (The H8S/2695 is not equipped with an IrDA function) H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Bit 6—Module Stop (MSTPB6): Specifies the SCI1 module stop mode. Bit 6 MSTPB6 Description 0 SCI1 module stop mode is cleared 1 SCI1 module stop mode is set (Initial value) Bit 5—Module Stop (MSTPB5): Specifies the SCI2 module stop mode.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 16.3 Operation 16.3.1 Overview Section 16 Serial Communication Interface (SCI, IrDA) (The H8S/2695 is not equipped with an IrDA function) The SCI can carry out serial communication in two modes: asynchronous mode in which synchronization is achieved character by character, and clocked synchronous mode in which synchronization is achieved with clock pulses.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 16 Serial Communication Interface (SCI, IrDA) (The H8S/2695 is not equipped with an IrDA function) Table 16.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 16.3.2 Section 16 Serial Communication Interface (SCI, IrDA) (The H8S/2695 is not equipped with an IrDA function) Operation in Asynchronous Mode In asynchronous mode, characters are sent or received, each preceded by a start bit indicating the start of communication and stop bits indicating the end of communication. Serial communication is thus carried out with synchronization established on a character-by-character basis.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 16 Serial Communication Interface (SCI, IrDA) (The H8S/2695 is not equipped with an IrDA function) Data Transfer Format Table 16.10 shows the data transfer formats that can be used in asynchronous mode. Any of 12 transfer formats can be selected according to the SMR setting. Table 16.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 16 Serial Communication Interface (SCI, IrDA) (The H8S/2695 is not equipped with an IrDA function) Clock Either an internal clock generated by the on-chip baud rate generator or an external clock input at the SCK pin can be selected as the SCI’s serial clock, according to the setting of the C/A bit in SMR and the CKE1 and CKE0 bits in SCR. For details of SCI clock source selection, see table 16.9.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 16 Serial Communication Interface (SCI, IrDA) (The H8S/2695 is not equipped with an IrDA function) Data Transfer Operations SCI initialization (asynchronous mode): Before transmitting and receiving data, you should first clear the TE and RE bits in SCR to 0, then initialize the SCI as described below. When the operating mode, transfer format, etc.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 16 Serial Communication Interface (SCI, IrDA) (The H8S/2695 is not equipped with an IrDA function) Serial data transmission (asynchronous mode): Figure 16.5 shows a sample flowchart for serial transmission. The following procedure should be used for serial data transmission.
Section 16 Serial Communication Interface (SCI, IrDA) (The H8S/2695 is not equipped with an IrDA function) H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 In serial transmission, the SCI operates as described below. [1] The SCI monitors the TDRE flag in SSR, and if is 0, recognizes that data has been written to TDR, and transfers the data from TDR to TSR. [2] After transferring data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts transmission.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 16 Serial Communication Interface (SCI, IrDA) (The H8S/2695 is not equipped with an IrDA function) Figure 16.6 shows an example of the operation for transmission in asynchronous mode.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 16 Serial Communication Interface (SCI, IrDA) (The H8S/2695 is not equipped with an IrDA function) Serial data reception (asynchronous mode): Figure 16.7 shows a sample flowchart for serial reception. The following procedure should be used for serial data reception. Initialization [1] Start reception [1] SCI initialization: The RxD pin is automatically designated as the receive data input pin.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 16 Serial Communication Interface (SCI, IrDA) (The H8S/2695 is not equipped with an IrDA function) [3] Error processing No ORER= 1 Yes Overrun error processing No FER= 1 Yes Yes Break? No Framing error processing Clear RE bit in SCR to 0 No PER= 1 Yes Parity error processing Clear ORER, PER, and FER flags in SSR to 0 Figure 16.7 Sample Serial Reception Data Flowchart (cont) R01UH0166EJ0600 Rev. 6.
Section 16 Serial Communication Interface (SCI, IrDA) (The H8S/2695 is not equipped with an IrDA function) H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 In serial reception, the SCI operates as described below. [1] The SCI monitors the transmission line, and if a 0 stop bit is detected, performs internal synchronization and starts reception. [2] The received data is stored in RSR in LSB-to-MSB order. [3] The parity bit and stop bit are received.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Table 16.11 Section 16 Serial Communication Interface (SCI, IrDA) (The H8S/2695 is not equipped with an IrDA function) Receive Errors and Conditions for Occurrence Receive Error Abbreviation Occurrence Condition Data Transfer Overrun error ORER When the next data reception is Receive data is not completed while the RDRF flag in transferred from RSR to SSR is set to 1 RDR.
Section 16 Serial Communication Interface (SCI, IrDA) (The H8S/2695 is not equipped with an IrDA function) 16.3.3 H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Multiprocessor Communication Function The multiprocessor communication function performs serial communication using the multiprocessor format, in which a multiprocessor bit is added to the transfer data, in asynchronous mode.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 16 Serial Communication Interface (SCI, IrDA) (The H8S/2695 is not equipped with an IrDA function) Clock See the section on asynchronous mode.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 16 Serial Communication Interface (SCI, IrDA) (The H8S/2695 is not equipped with an IrDA function) [1] [1] SCI initialization: Initialization Start transmission Read TDRE flag in SSR [2] No TDRE= 1 Yes Write transmit data to TDR and set MPBT bit in SSR Clear TDRE flag to 0 No All data transmitted? Yes Read TEND flag in SSR No TEND= 1 Yes No Break output? The TxD pin is automatically designated as the transmit data output pi
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 16 Serial Communication Interface (SCI, IrDA) (The H8S/2695 is not equipped with an IrDA function) In serial transmission, the SCI operates as described below. [1] The SCI monitors the TDRE flag in SSR, and if is 0, recognizes that data has been written to TDR, and transfers the data from TDR to TSR. [2] After transferring data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts transmission.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 16 Serial Communication Interface (SCI, IrDA) (The H8S/2695 is not equipped with an IrDA function) Figure 16.11 shows an example of SCI operation for transmission using the multiprocessor format.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 16 Serial Communication Interface (SCI, IrDA) (The H8S/2695 is not equipped with an IrDA function) Multiprocessor serial data reception: Figure 16.12 shows a sample flowchart for multiprocessor serial reception. The following procedure should be used for multiprocessor serial data reception. Initialization [1] [1] SCI initialization: The RxD pin is automatically designated as the receive data input pin.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 16 Serial Communication Interface (SCI, IrDA) (The H8S/2695 is not equipped with an IrDA function) [5] Error processing No ORER= 1 Yes Overrun error processing No FER= 1 Yes Yes Break? No Framing error processing Clear RE bit in SCR to 0 Clear ORER, PER, and FER flags in SSR to 0 Figure 16.12 Sample Multiprocessor Serial Reception Flowchart (cont) Page 776 of 1434 R01UH0166EJ0600 Rev. 6.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 16 Serial Communication Interface (SCI, IrDA) (The H8S/2695 is not equipped with an IrDA function) Figure 16.13 shows an example of SCI operation for multiprocessor format reception.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 16 Serial Communication Interface (SCI, IrDA) (The H8S/2695 is not equipped with an IrDA function) 16.3.4 Operation in Clocked Synchronous Mode In clocked synchronous mode, data is transmitted or received in synchronization with clock pulses, making it suitable for high-speed serial communication. Inside the SCI, the transmitter and receiver are independent units, enabling full-duplex communication by use of a common clock.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 16 Serial Communication Interface (SCI, IrDA) (The H8S/2695 is not equipped with an IrDA function) Data Transfer Format A fixed 8-bit data format is used. No parity or multiprocessor bits are added. Clock Either an internal clock generated by the on-chip baud rate generator or an external serial clock input at the SCK pin can be selected, according to the setting of the C/A bit in SMR and the CKE1 and CKE0 bits in SCR.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 16 Serial Communication Interface (SCI, IrDA) (The H8S/2695 is not equipped with an IrDA function) Data Transfer Operations SCI initialization (clocked synchronous mode): Before transmitting and receiving data, you should first clear the TE and RE bits in SCR to 0, then initialize the SCI as described below. When the operating mode, transfer format, etc.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 16 Serial Communication Interface (SCI, IrDA) (The H8S/2695 is not equipped with an IrDA function) Serial data transmission (clocked synchronous mode): Figure 16.16 shows a sample flowchart for serial transmission. The following procedure should be used for serial data transmission.
Section 16 Serial Communication Interface (SCI, IrDA) (The H8S/2695 is not equipped with an IrDA function) H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 In serial transmission, the SCI operates as described below. [1] The SCI monitors the TDRE flag in SSR, and if is 0, recognizes that data has been written to TDR, and transfers the data from TDR to TSR. [2] After transferring data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts transmission.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 16 Serial Communication Interface (SCI, IrDA) (The H8S/2695 is not equipped with an IrDA function) Figure 16.17 shows an example of SCI operation in transmission.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 16 Serial Communication Interface (SCI, IrDA) (The H8S/2695 is not equipped with an IrDA function) [1] Initialization Start reception [2] Read ORER flag in SSR Yes [3] ORER= 1 No Error processing (Continued below) Read RDRF flag in SSR [4] No RDRF= 1 Yes Read receive data in RDR, and clear RDRF flag in SSR to 0 No All data received? Yes Clear RE bit in SCR to 0 [5] [1] SCI initialization: The RxD pin is automatically de
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 16 Serial Communication Interface (SCI, IrDA) (The H8S/2695 is not equipped with an IrDA function) In serial reception, the SCI operates as described below. [1] The SCI performs internal initialization in synchronization with serial clock input or output. [2] The received data is stored in RSR in LSB-to-MSB order. After reception, the SCI checks whether the RDRF flag is 0 and the receive data can be transferred from RSR to RDR.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 16 Serial Communication Interface (SCI, IrDA) (The H8S/2695 is not equipped with an IrDA function) Initialization [1] SCI initialization: [1] The TxD pin is designated as the transmit data output pin, and the RxD pin is designated as the receive data input pin, enabling simultaneous transmit and receive operations.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 16.3.5 Section 16 Serial Communication Interface (SCI, IrDA) (The H8S/2695 is not equipped with an IrDA function) IrDA Operation Figure 16.21 is a block diagram of the IrDA. When the IrE bit of IrCR is set to enable the IrDA function, the TxD0/RxD0 signals of SCI channel 0 are encoded and decoded with waveforms conforming to the IrDA standard version 1.0 (IrTxD/IrRxD pins).
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 16 Serial Communication Interface (SCI, IrDA) (The H8S/2695 is not equipped with an IrDA function) As per the standard, the High pulse width is a minimum of 1.41 µs, the maximum is (3/16 + 2.5%) × bit rate, or (3/16 × bit rate) + 1.08 µs. With a 20MHz system clock φ, the minimum High pulse width can be set to 1.6 µs, which is greater than the 1.41 µs required by the standard.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Table 16.12 Section 16 Serial Communication Interface (SCI, IrDA) (The H8S/2695 is not equipped with an IrDA function) Setting Bits IrCKS2 to IrCKS0 Bit Rate (bps) (Upper Row) / Bit Cycle × 3/16 (µs) (Lower Row) 2400 9600 19200 38400 57600 115200 Operating Frequency (MHz) 78.13 19.53 9.77 4.88 3.26 1.63 2 010 010 010 010 010 — 2.097152 010 010 010 010 010 — 2.
Section 16 Serial Communication Interface (SCI, IrDA) (The H8S/2695 is not equipped with an IrDA function) 16.4 H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 SCI Interrupts The SCI has four interrupt sources: the transmit-end interrupt (TEI) request, receive-error interrupt (ERI) request, receive-data-full interrupt (RXI) request, and transmit-data-empty interrupt (TXI) request. Table 16.13 shows the interrupt sources and their relative priorities.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Table 16.
Section 16 Serial Communication Interface (SCI, IrDA) (The H8S/2695 is not equipped with an IrDA function) H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 A TEI interrupt is requested when the TEND flag is set to 1 while the TEIE bit is set to 1. The TEND flag is cleared at the same time as the TDRE flag.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 16 Serial Communication Interface (SCI, IrDA) (The H8S/2695 is not equipped with an IrDA function) Break Detection and Processing (Asynchronous Mode Only): When framing error (FER) detection is performed, a break can be detected by reading the RxD pin value directly. In a break, the input from the RxD pin becomes all 0s, and so the FER flag is set, and the parity error flag (PER) may also be set.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 16 Serial Communication Interface (SCI, IrDA) (The H8S/2695 is not equipped with an IrDA function) 16 clocks 8 clocks 0 7 15 0 7 15 0 Internal basic clock Receive data (RxD) Start bit D0 D1 Synchronization sampling timing Data sampling timing Figure 16.23 Receive Data Sampling Timing in Asynchronous Mode Thus the reception margin in asynchronous mode is given by formula (1) below. 1 2N M =⎮(0.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 16 Serial Communication Interface (SCI, IrDA) (The H8S/2695 is not equipped with an IrDA function) Restrictions on Use of DMAC* or DTC* • When an external clock source is used as the serial clock, the transmit clock should not be input until at least 5 φ clock cycles after TDR is updated by the DMAC or DTC. Misoperation may occur if the transmit clock is input within 4 φ clocks after TDR is updated. (Figure 16.
Section 16 Serial Communication Interface (SCI, IrDA) (The H8S/2695 is not equipped with an IrDA function) H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Operation in Case of Mode Transition • Transmission Operation should be stopped (by clearing TE, TIE, and TEIE to 0) before making a module stop mode, software standby mode, watch mode, subactive mode, or subsleep mode transition. TSR, TDR, and SSR are reset.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 16 Serial Communication Interface (SCI, IrDA) (The H8S/2695 is not equipped with an IrDA function) No All data transmitted? [1] Yes Read TEND flag in SSR No TEND = 1 Yes TE= 0 [2] If TIE and TEIE are set to 1, clear them to 0 in the same way. [2] Transition to software standby mode, etc. [3] Exit from software standby mode, etc. Change operating mode? [1] Data being transmitted is interrupted.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 16 Serial Communication Interface (SCI, IrDA) (The H8S/2695 is not equipped with an IrDA function) End of transmission Start of transmission Transition to software standby Exit from software standby TE bit Port input/output SCK output pin TxD output pin Port input/output High output Port Start Stop Port input/output Port SCI TxD output High output SCI TxD output Figure 16.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 16 Serial Communication Interface (SCI, IrDA) (The H8S/2695 is not equipped with an IrDA function) Read RDRF flag in SSR RDRF= 1 No [1] [1] Receive data being received becomes invalid. [2] [2] Includes module stop mode, watch mode*, subactive mode*, and subsleep mode*. Yes Read receive data in RDR RE= 0 Transition to software standby mode, etc. Exit from software standby mode, etc.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 16 Serial Communication Interface (SCI, IrDA) (The H8S/2695 is not equipped with an IrDA function) Switching from SCK Pin Function to Port Pin Function • Problem in Operation: When switching the SCK pin to the output function while DDR and DR are set to 1 and clock synchronous SCI clock output is being used, low-level output occurs for one half-cycle, followed by port output.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 16 Serial Communication Interface (SCI, IrDA) (The H8S/2695 is not equipped with an IrDA function) • Sample Procedure for Avoiding Low-Level Output: As this sample procedure temporarily places the SCK pin in the input state, the SCK/port pin should be pulled up beforehand with an external circuit. With DDR = 1, DR = 1, C/A = 1, CKE1 = 0, CKE0 = 0, and TE = 1, make the following settings in the order shown. 1.
Section 16 Serial Communication Interface (SCI, IrDA) (The H8S/2695 is not equipped with an IrDA function) Page 802 of 1434 H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 R01UH0166EJ0600 Rev. 6.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 17 Smart Card Interface Section 17 Smart Card Interface 17.1 Overview SCI supports an IC card (Smart Card) interface conforming to ISO/IEC 7816-3 (Identification Card) as a serial communication interface extension function. Switching between the normal serial communication interface and the Smart Card interface is carried out by means of a register setting. 17.1.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 17 Smart Card Interface 17.1.2 Block Diagram Bus interface Figure 17.1 shows a block diagram of the Smart Card interface.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 17.1.3 Section 17 Smart Card Interface Pin Configuration Table 17.1 shows the Smart Card interface pin configuration. Table 17.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 17 Smart Card Interface 17.1.4 Register Configuration Table 17.2 shows the registers used by the Smart Card interface. Details of BRR, TDR, RDR, and MSTPCR are the same as for the normal SCI function: see the register descriptions in section 16, Serial Communication Interface (SCI, IrDA). Table 17.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 17 Smart Card Interface Channel Name Abbreviation R/W Initial Value Address* 3 Serial mode register 3 SMR3 R/W H'00 H'FDD0 Bit rate register 3 BRR3 R/W H'FF H'FDD1 Serial control register 3 SCR3 R/W H'00 H'FDD2 Transmit data register 3 TDR3 R/W H'FF H'FDD3 Serial status register 3 SSR3 2 R/(W)* H'84 H'FDD4 Receive data register 3 RDR3 R H'00 H'FDD5 Smart card mode register 3 SCMR3 R/W H'F2
Section 17 Smart Card Interface H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 SCMR is initialized to H'F2 by a reset and in hardware standby mode. Bits 7 to 4—Reserved: These bits are always read as 1 and cannot be modified. Bit 3—Smart Card Data Transfer Direction (SDIR): Selects the serial/parallel conversion format.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 17.2.2 Section 17 Smart Card Interface Serial Status Register (SSR) Bit : Initial value : R/W : 7 6 5 4 3 2 1 0 TDRE RDRF ORER ERS PER TEND MPB MPBT 1 0 0 0 0 1 0 0 R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R R R/W Note: * Only 0 can be written, to clear these flags. Bit 4 of SSR has a different function in Smart Card interface mode.
Section 17 Smart Card Interface H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Bits 3 to 0—Operate in the same way as for the normal SCI. For details, see section 16.2.7, Serial Status Register (SSR). However, the setting conditions for the TEND bit, are as shown below.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 17.2.3 Section 17 Smart Card Interface Serial Mode Register (SMR) Bit : Initial value : R/W : 7 6 5 4 3 2 1 0 GM BLK PE O/E BCP1 BCP0 CKS1 CKS0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Note: When the smart card interface is used, be sure to make the 1 setting shown for bit 5. The function of bits 7, 6, 3, and 2 of SMR changes in Smart Card interface mode.
Section 17 Smart Card Interface H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Bit 6—Block Transfer Mode (BLK): Selects block transfer mode. Bit 6 BLK Description 0 Normal Smart Card interface mode operation • • • 1 Error signal transmission/detection and automatic data retransmission performed TXI interrupt generated by TEND flag TEND flag set 12.5 etu after start of transmission (11.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 17.2.4 Section 17 Smart Card Interface Serial Control Register (SCR) Bit : Initial value : R/W : 7 6 5 4 3 2 1 0 TIE RIE TE RE MPIE TEIE CKE1 CKE0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W In smart card interface mode, the function of bits 1 and 0 of SCR changes when bit 7 of the serial mode register (SMR) is set to 1. Bits 7 to 2—Operate in the same way as for the normal SCI.
Section 17 Smart Card Interface 17.3 Operation 17.3.1 Overview H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 The main functions of the Smart Card interface are as follows. • One frame consists of 8-bit data plus a parity bit. • In transmission, a guard time of at least 2 etu (1 etu in the block transfer mode) is left between the end of the parity bit and the start of the next frame.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 17.3.2 Section 17 Smart Card Interface Pin Connections Figure 17.2 shows a schematic diagram of Smart Card interface related pin connections. In communication with an IC card, since both transmission and reception are carried out on a single data transmission line, the TxD pin and RxD pin should be connected with the LSI pin. The data transmission line should be pulled up to the VCC power supply with a resistor.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 17 Smart Card Interface 17.3.3 Data Format (1) Normal Transfer Mode Figure 17.3 shows the normal Smart Card interface data format. In reception in this mode, a parity check is carried out on each frame, and if an error is detected an error signal is sent back to the transmitting end, and retransmission of the data is requested. If an error signal is sampled during transmission, the same data is retransmitted.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 17 Smart Card Interface The operation sequence is as follows. [1] When the data line is not in use it is in the high-impedance state, and is fixed high with a pullup resistor. [2] The transmitting station starts transfer of one frame of data. The data frame starts with a start bit (Ds, low-level), followed by 8 data bits (D0 to D7) and a parity bit (Dp).
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 17 Smart Card Interface 17.3.4 Register Settings Table 17.3 shows a bit map of the registers used by the smart card interface. Bits indicated as 0 or 1 must be set to the value shown. The setting of other bits is described below. Table 17.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 17 Smart Card Interface Smart Card Mode Register (SCMR) Setting: The SDIR bit is cleared to 0 if the IC card is of the direct convention type, and set to 1 if of the inverse convention type. The SINV bit is cleared to 0 if the IC card is of the direct convention type, and set to 1 if of the inverse convention type. The SMIF bit is set to 1 in the case of the Smart Card interface.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 17 Smart Card Interface 17.3.5 Clock Only an internal clock generated by the on-chip baud rate generator can be used as the transmit/receive clock for the smart card interface. The bit rate is set with BRR and the CKS1, CKS0, BCP1 and BCP0 bits in SMR. The formula for calculating the bit rate is as shown below. Table 17.5 shows some sample bit rates.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 17 Smart Card Interface The method of calculating the value to be set in the bit rate register (BRR) from the operating frequency and bit rate, on the other hand, is shown below. N is an integer, 0 ≤ N ≤ 255, and the smaller error is specified. N= φ S×2 × 10 – 1 6 2n+1 ×B Table 17.6 Examples of BRR Settings for Bit Rate B (bit/s) (When n = 0 and S = 372) φ (MHz) 7.1424 10.00 10.7136 13.00 14.2848 16.00 18.00 20.
Section 17 Smart Card Interface 17.3.6 H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Data Transfer Operations Initialization: Before transmitting and receiving data, initialize the SCI as described below. Initialization is also necessary when switching from transmit mode to receive mode, or vice versa. [1] Clear the TE and RE bits in SCR to 0. [2] Clear the error flags ERS, PER, and ORER in SSR to 0. [3] Set the GM, BLK, O/E, BCP1, BCP0, CKS1, and CKS0 bits in SMR.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 17 Smart Card Interface Serial Data Transmission (Except Block Transfer Mode): As data transmission in smart card mode involves error signal sampling and retransmission processing, the processing procedure is different from that for the normal SCI. Figure 17.4 shows a flowchart for transmitting, and figure 17.5 shows the relation between a transmit operation and the internal registers.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 17 Smart Card Interface Start Initialization Start transmission ERS=0? No Yes Error processing No TEND=1? Yes Write data to TDR, and clear TDRE flag in SSR to 0 No All data transmitted? Yes No ERS=0? Yes Error processing No TEND=1? Yes Clear TE bit to 0 End Figure 17.4 Example of Transmission Processing Flow Page 824 of 1434 R01UH0166EJ0600 Rev. 6.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 17 Smart Card Interface TSR (shift register) TDR (1) Data write Data 1 (2) Transfer from TDR to TSR Data 1 (3) Serial data output Data 1 Data 1 ; Data remains in TDR Data 1 I/O signal line output In case of normal transmission: TEND flag is set In case of transmit error: ERS flag is set Steps (2) and (3) above are repeated until the TEND flag is set Note: When the ERS flag is set, it should be cleared until transfer of
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 17 Smart Card Interface Serial Data Reception (Except Block Transfer Mode): Data reception in Smart Card mode uses the same processing procedure as for the normal SCI. Figure 17.7 shows an example of the transmission processing flow. [1] Perform Smart Card interface mode initialization as described above in Initialization. [2] Check that the ORER flag and PER flag in SSR are cleared to 0.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 17 Smart Card Interface With the above processing, interrupt servicing or data transfer by the DMAC* or DTC* is possible. If reception ends and the RDRF flag is set to 1 while the RIE bit is set to 1 and interrupt requests are enabled, a receive data full interrupt (RXI) request will be generated.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 17 Smart Card Interface Specified pulse width Specified pulse width SCK SCR write (CKE0 = 0) SCR write (CKE0 = 1) Figure 17.8 Timing for Fixing Clock Output Level Interrupt Operation (Except Block Transfer Mode): There are three interrupt sources in smart card interface mode: transmit data empty interrupt (TXI) requests, transfer error interrupt (ERI) requests, and receive data full interrupt (RXI) requests.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 17 Smart Card Interface Data Transfer Operation by DMAC* or DTC*: In smart card mode, as with the normal SCI, transfer can be carried out using the DMAC* or DTC*. In a transmit operation, the TDRE flag is also set to 1 at the same time as the TEND flag in SSR, and a TXI interrupt is generated.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 17 Smart Card Interface 17.3.7 Operation in GSM Mode Switching the Mode: When switching between smart card interface mode and software standby mode, the following switching procedure should be followed in order to maintain the clock duty.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 17 Smart Card Interface Powering On: To secure the clock duty from power-on, the following switching procedure should be followed. [1] The initial state is port input and high impedance. Use a pull-up resistor or pull-down resistor to fix the potential. [2] Fix the SCK pin to the specified output level with the CKE1 bit in SCR. [3] Set SMR and SCMR, and switch to smart card mode operation.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 17 Smart Card Interface 17.4 Usage Notes The following points should be noted when using the SCI as a Smart Card interface. Receive Data Sampling Timing and Reception Margin in Smart Card Interface Mode: In Smart Card interface mode, the SCI operates on a basic clock with a frequency of 32, 64, 372, or 256 times the transfer rate (as determined by bits BCP1 and BCP0).
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 17 Smart Card Interface Thus the reception margin in asynchronous mode is given by the following formula. Formula for reception margin in smart card interface mode M =⎮(0.5 – Where M: N: D: L: F: 1 2N ) – (L – 0.5) F – | D – 0.5 | (1 + F)⎮ × 100% N Reception margin (%) Ratio of bit rate to clock (N = 32, 64, 372, and 256) Clock duty (D = 0 to 1.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 17 Smart Card Interface Retransfer Operations (Except Block Transfer Mode): Retransfer operations are performed by the SCI in receive mode and transmit mode as described below. • Retransfer operation when SCI is in receive mode Figure 17.11 illustrates the retransfer operation when the SCI is in receive mode. [1] If an error is found when the received parity bit is checked, the PER bit in SSR is automatically set to 1.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 17 Smart Card Interface • Retransfer operation when SCI is in transmit mode Figure 17.12 illustrates the retransfer operation when the SCI is in transmit mode. [6] If an error signal is sent back from the receiving end after transmission of one frame is completed, the ERS bit in SSR is set to 1. If the RIE bit in SCR is enabled at this time, an ERI interrupt request is generated.
Section 17 Smart Card Interface Page 836 of 1434 H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 R01UH0166EJ0600 Rev. 6.
TM 2 H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 18 I C Bus Interface [Option] (This function is not available in the H8S/2695) 2 Section 18 I C Bus Interface [Option] (This function is not available in the H8S/2695) 2 2 A two-channel I C bus interface is available as an option in the H8S/2633 Group. The I C bus interface is not available for the H8S/2633 Group. Observe the following notes when using this option. 1.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 2 Section 18 I C Bus Interface [Option] (This function is not available in the H8S/2695) • Wait function in slave mode (I C bus format) 2 A wait request can be generated by driving the SCL pin low after data transfer, excluding acknowledgement. The wait request is cleared when the next transfer becomes possible.
TM 2 H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 φ Section 18 I C Bus Interface [Option] (This function is not available in the H8S/2695) PS ICCR SCL Clock control Noise canceler Bus state decision circuit SDA ICSR Arbitration decision circuit ICDRT Output data control circuit ICDRS Internal data bus ICMR ICDRR Noise canceler Address comparator SAR, SARX Interrupt generator Legend: ICCR: I2C bus control register ICMR: I2C bus mode register ICSR: I2C bus status registe
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 2 Section 18 I C Bus Interface [Option] (This function is not available in the H8S/2695) VDD PVCC2 SCL SCL SDA SDA SCL in SDA out (Master) SCL in H8S/2633 Group chip SCL out SCL out SDA in SDA in SDA out SDA out SCL SDA SDA in SCL SDA SCL out SCL in (Slave 1) (Slave 2) 2 Figure 18.2 I C Bus Interface Connections (Example: H8S/2633 Group Chip as Master) 18.1.3 Input/Output Pins 2 Table 18.
TM 2 H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 18.1.4 Section 18 I C Bus Interface [Option] (This function is not available in the H8S/2695) Register Configuration 2 Table 18.2 summarizes the registers of the I C bus interface. Table 18.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 2 Section 18 I C Bus Interface [Option] (This function is not available in the H8S/2695) 18.2 Register Descriptions 18.2.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 2 Section 18 I C Bus Interface [Option] (This function is not available in the H8S/2695) ICDR is an 8-bit readable/writable register that is used as a transmit data register when transmitting and a receive data register when receiving. ICDR is divided internally into a shift register (ICDRS), receive buffer (ICDRR), and transmit buffer (ICDRT). ICDRS cannot be read or written by the CPU, ICDRR is read-only, and ICDRT is write-only.
2 Section 18 I C Bus Interface [Option] (This function is not available in the H8S/2695) H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 TDRE Description 0 The next transmit data is in ICDR (ICDRT), or transmission cannot be started (Initial value) [Clearing conditions] • • • • 1 When transmit data is written in ICDR (ICDRT) in transmit mode (TRS = 1) When a stop condition is detected in the bus line state after a stop condition is 2 issued with the I C bus format or serial forma
TM 2 H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 18.2.2 Section 18 I C Bus Interface [Option] (This function is not available in the H8S/2695) Slave Address Register (SAR) Bit : Initial value : R/W : 7 6 5 4 3 2 1 0 SVA6 SVA5 SVA4 SVA3 SVA2 SVA1 SVA0 FS 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W SAR is an 8-bit readable/writable register that stores the slave address and selects the communication format.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 2 Section 18 I C Bus Interface [Option] (This function is not available in the H8S/2695) SAR Bit 0 SARX Bit 0 FS FSX Operating Mode 0 0 I C bus format 2 • I C bus format • • 1 (Initial value) SAR slave address recognized SARX slave address ignored 2 0 I C bus format • • 1 SAR slave address ignored SARX slave address recognized Synchronous serial format • 18.2.
TM 2 H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 18 I C Bus Interface [Option] (This function is not available in the H8S/2695) The FSX bit also specifies whether or not SARX slave address recognition is performed in slave mode. For details, see the description of the FS bit in SAR. 18.2.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 2 Section 18 I C Bus Interface [Option] (This function is not available in the H8S/2695) The IRIC flag in ICCR is set to 1 on completion of the acknowledge bit transfer, regardless of the WAIT setting. The setting of this bit is invalid in slave mode.
TM 2 H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 18 I C Bus Interface [Option] (This function is not available in the H8S/2695) Bits 2 to 0—Bit Counter (BC2 to BC0): Bits BC2 to BC0 specify the number of bits to be 2 transferred next. With the I C bus format (when the FS bit in SAR or the FSX bit in SARX is 0), the data is transferred with one addition acknowledge bit. Bit BC2 to BC0 settings should be made during an interval between transfer frames.
2 Section 18 I C Bus Interface [Option] (This function is not available in the H8S/2695) 2 H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 2 Bit 7—I C Bus Interface Enable (ICE): Selects whether or not the I C bus interface is to be used. When ICE is set to 1, port pins function as SCL and SDA input/output pins and transfer 2 operations are enabled. When ICE is cleared to 0, the I C bus interface module is halted and its internal states are cleared.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 2 Section 18 I C Bus Interface [Option] (This function is not available in the H8S/2695) Bit 5—Master/Slave Select (MST) Bit 4—Transmit/Receive Select (TRS) 2 MST selects whether the I C bus interface operates in master mode or slave mode. 2 TRS selects whether the I C bus interface operates in transmit mode or receive mode.
2 Section 18 I C Bus Interface [Option] (This function is not available in the H8S/2695) H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Bit 4 TRS Description 0 Receive mode (Initial value) [Clearing conditions] 1. When 0 is written by software (in cases other than setting condition 3) 2. When 0 is written in TRS after reading TRS = 1 (in case of clearing condition 3) 2 3.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 2 Section 18 I C Bus Interface [Option] (This function is not available in the H8S/2695) Bit 3 ACKE Description 0 The value of the acknowledge bit is ignored, and continuous transfer is performed 1 (Initial value) If the acknowledge bit is 1, continuous transfer is interrupted 2 Bit 2—Bus Busy (BBSY): The BBSY flag can be read to check whether the I C bus (SCL, SDA) is busy or free.
2 Section 18 I C Bus Interface [Option] (This function is not available in the H8S/2695) 2 H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 2 Bit 1—I C Bus Interface Interrupt Request Flag (IRIC): Indicates that the I C bus interface has issued an interrupt request to the CPU.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 2 Section 18 I C Bus Interface [Option] (This function is not available in the H8S/2695) Bit 1 IRIC Description 0 Waiting for transfer, or transfer in progress (Initial value) [Clearing conditions] 1. When 0 is written in IRIC after reading IRIC = 1 2.
2 Section 18 I C Bus Interface [Option] (This function is not available in the H8S/2695) H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 2 When, with the I C bus format selected, IRIC is set to 1 and an interrupt is generated, other flags must be checked in order to identify the source that set IRIC to 1. Although each source has a corresponding flag, caution is needed at the end of a transfer. When the TDRE or RDRF internal flag is set, the readable IRTR flag may or may not be set.
TM 2 H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 18 I C Bus Interface [Option] (This function is not available in the H8S/2695) Table 18.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 2 Section 18 I C Bus Interface [Option] (This function is not available in the H8S/2695) 18.2.6 2 I C Bus Status Register (ICSR) Bit : Initial value : R/W : 7 6 5 4 3 2 1 0 ESTP STOP IRTR AASX AL AAS ADZ ACKB 0 0 0 0 0 0 0 0 R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/W Note: * Only 0 can be written, for flag clearing.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 2 Section 18 I C Bus Interface [Option] (This function is not available in the H8S/2695) Bit 6 STOP Description 0 No normal stop condition (Initial value) [Clearing conditions] 1. When 0 is written in STOP after reading STOP = 1 2.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 2 Section 18 I C Bus Interface [Option] (This function is not available in the H8S/2695) 2 Bit 4—Second Slave Address Recognition Flag (AASX): In I C bus format slave receive mode, this flag is set to 1 if the first frame following a start condition matches bits SVAX6 to SVAX0 in SARX. AASX is cleared by reading AASX after it has been set to 1, then writing 0 in AASX. AASX is also cleared automatically when a start condition is detected.
TM 2 H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 18 I C Bus Interface [Option] (This function is not available in the H8S/2695) 2 Bit 2—Slave Address Recognition Flag (AAS): In I C bus format slave receive mode, this flag is set to 1 if the first frame following a start condition matches bits SVA6 to SVA0 in SAR, or if the general call address (H'00) is detected. AAS is cleared by reading AAS after it has been set to 1, then writing 0 in AAS.
2 Section 18 I C Bus Interface [Option] (This function is not available in the H8S/2695) H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Bit 0—Acknowledge Bit (ACKB): Stores acknowledge data. In transmit mode, after the receiving device receives data, it returns acknowledge data, and this data is loaded into ACKB. In receive mode, after data has been received, the acknowledge data set in this bit is sent to the transmitting device.
TM 2 H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 18.2.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 2 Section 18 I C Bus Interface [Option] (This function is not available in the H8S/2695) 18.2.8 DDC Switch Register (DDCSWR) Bit : Initial value : 7 6 5 4 3 2 1 0 — — — — CLR3 CLR2 CLR1 CLR0 0 0 0 0 : R/(W)*1 R/W R/(W)*1 R/(W)*1 R/(W)*1 1 1 1 1 W*2 W*2 W*2 W*2 Notes: 1. Should always be written with 0. 2. Always read as 1.
TM 2 H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 18.2.9 Section 18 I C Bus Interface [Option] (This function is not available in the H8S/2695) Module Stop Control Register B (MSTPCRB) Bit : 7 6 5 4 3 2 1 0 MSTPB7 MSTPB6 MSTPB5 MSTPB4 MSTPB3 MSTPB2 MSTPB1 MSTPB0 Initial value : R/W : 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W MSTPCRB is an 8-bit readable/writable register that perform module stop mode control.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 2 Section 18 I C Bus Interface [Option] (This function is not available in the H8S/2695) 18.3 Operation 18.3.1 I C Bus Data Format 2 2 2 The I C bus interface has serial and I C bus formats. 2 The I C bus formats are addressing formats with an acknowledge bit. These are shown in figures 18.3 (a) and (b). The first frame following a start condition always consists of 8 bits.
TM 2 H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 18 I C Bus Interface [Option] (This function is not available in the H8S/2695) FS = 1 and FSX = 1 S DATA DATA P 1 8 n 1 1 m n: transfer bit count (n = 1 to 8) m: transfer frame count (m ≥ 1) 2 Figure 18.4 I C Bus Data Format (Serial Format) SDA SCL S 1-7 8 9 SLA R/W A 1-7 8 DATA 9 A 1-7 8 DATA 9 A/A P 2 Figure 18.5 I C Bus Timing 2 Table 18.
2 Section 18 I C Bus Interface [Option] (This function is not available in the H8S/2695) 18.3.2 H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Initial Setting At startup the following procedure is used to initialize the IIC. Start initialization Set MSTP4 = 0 (IIC0) MSTP3 = 0 (IIC1) (MSTPCRL) Clear module stop. Set IICE = 1 (STCR) Enable CPU access by IIC control register and data register. Set DDCSWR Clear IIC internal latch Set ICE = 0 (ICCR) Enable SAR and SARX access.
TM 2 H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 18 I C Bus Interface [Option] (This function is not available in the H8S/2695) Start [1] Initial settings. Initial settings Read BBSY flag in ICCR [2] Determine status of SCL and SDA lines. No BBSY = 0? Yes Set MST = 1 and TRS = 1 (ICCR) [3] Set to master transmit mode. Write BBSY = 1 and SCP = 0 (ICCR) [4] Generate start condition. Read IRIC flag in ICCR [5] Wait for start condition to be met.
2 Section 18 I C Bus Interface [Option] (This function is not available in the H8S/2695) H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 The procedure for transmitting data sequentially, synchronized with ICDR (ICDRT) write operations, is described below. [1] Perform initial settings as described in section 18.3.2, Initial Setting. [2] Read the BBSY flag in ICCR to confirm that the bus is free. [3] Set bits MST and TSR in ICCR to 1 to switch to the master transmit mode.
TM 2 H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 18 I C Bus Interface [Option] (This function is not available in the H8S/2695) [11] Read the ACKB bit in ICSR to confirm that the slave device has returned an acknowledge signal and the value of ACKB is 0. If the slave device has not returned an acknowledge signal and the value of ACKB is 1, perform the transmit end processing described in step [12]. [12] Clear the IRIC flag to 0.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 2 Section 18 I C Bus Interface [Option] (This function is not available in the H8S/2695) Generate start condition SCL (Master output) 8 SDA (Master output) 9 Bit 0 Data 1 SDA (Slave output) 1 Bit 7 2 3 Bit 6 Bit 5 [7] 4 Bit 4 5 Bit 3 Data 2 A 6 Bit 2 7 8 9 Bit 1 Bit 0 [10] A ICDRE IRIC IRTR Data 1 ICDR User processing [9] ICDR write Data 2 [9] IRIC clearance [12] Write BBSY = 0 and SCP = 0 (generate stop condition
TM 2 H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 18 I C Bus Interface [Option] (This function is not available in the H8S/2695) Master receive mode Set TRS = 0 (ICCR) [1] Set to receive mode. Set ACKB = 0 (ICSR) Set WAIT = 1 (ICMR) Read ICDR [2] Receive start, dummy read. Read IRIC flag in ICCR No [3] Receive wait state (IRIC set at falling edge of 8th clock cycle) or Wait for end of reception of 1 byte (IRIC set at rising edge of 9th clock cycle).
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 2 Section 18 I C Bus Interface [Option] (This function is not available in the H8S/2695) Master receive mode Set TRS = 0 (ICCR) Set ACKB = 0 (ICSR) [1] Set to receive mode [2] Receive start, dummy read. [3] Receive wait state (IRIC set at falling edge of 8th clock cycle) or Wait for end of reception of 1 byte (IRIC set at rising edge of 9th clock cycle). Set ACKB = 1 (ICSR) [7] Set acknowledge data for final receive.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 2 Section 18 I C Bus Interface [Option] (This function is not available in the H8S/2695) [1] Clear the TRS bit in ICCR to 0 to switch from transmit mode to receive mode. Clear the ACKB bit in ICSR to 0 (acknowledge data setting). Then set the WAIT bit in ICMR to 1. [2] When ICDR is read (dummy data read), reception is started, and the receive clock is output, and data received, in synchronization with the internal clock.
2 Section 18 I C Bus Interface [Option] (This function is not available in the H8S/2695) H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 [12] The IRIC flag is set to 1 by the following two conditions. 1. The flag is set at the falling edge of the 8th clock cycle of the receive clock for 1 frame. SCL is automatically held low, in synchronization with the internal clock, until the IRIC flag is cleared. 2.
TM 2 H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Master transmit mode SCL (master output) 9 SDA (slave output) A Section 18 I C Bus Interface [Option] (This function is not available in the H8S/2695) Master receive mode 1 2 3 4 5 6 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 7 8 9 Bit 1 Bit 0 Data 1 1 2 3 4 5 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 [3] Data 2 [3] SDA (master output) A IRIC IRTR [4] IRTR = 0 [4] IRTR = 1 ICDR Data 1 User processing [6] IRIC clearance (
2 Section 18 I C Bus Interface [Option] (This function is not available in the H8S/2695) 18.3.5 H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Slave Receive Operation In slave receive mode, the master device outputs the transmit clock and transmit data, and the slave device returns an acknowledge signal. The slave device compares its own address with the slave address in the first frame following the establishment of the start condition issued by the master device.
TM 2 H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 18 I C Bus Interface [Option] (This function is not available in the H8S/2695) Start Initialize Set MST = 0 and TRS = 0 in ICCR [1] Set ACKB = 0 in ICSR Read IRIC in ICCR No [2] IRIC = 1? Yes Read AAS and ADZ in ICSR AAS = 1 and ADZ = 0? No General call address processing * Description omitted Yes Read TRS in ICCR No TRS = 0? Slave transmit mode Yes Last receive? No Read ICDR Yes [3] [1] Select slave receive mode C
2 Section 18 I C Bus Interface [Option] (This function is not available in the H8S/2695) H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 The reception procedure and operations in slave receive mode are described below. (1) Set the ICE bit in ICCR to 1. Set the MLS bit in ICMR and the MST and TRS bits in ICCR according to the operating mode. (2) When the start condition output by the master device is detected, the BBSY flag in ICCR is set to 1.
TM 2 H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 18 I C Bus Interface [Option] (This function is not available in the H8S/2695) Start condition issuance SCL (master output) 1 2 3 Bit 7 Bit 6 Bit 5 4 5 Bit 4 Bit 3 6 7 Bit 2 Bit 1 8 9 1 2 SCL (slave output) SDA (master output) SDA (slave output) Slave address Bit 0 R/W Bit 7 Bit 6 Data 1 [4] A RDRF Interrupt request generation IRIC ICDRS Address + R/W ICDRR Address + R/W User processing [5] I
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 2 Section 18 I C Bus Interface [Option] (This function is not available in the H8S/2695) SCL (master output) 7 8 Bit 1 Bit 0 9 1 2 Bit 7 Bit 6 3 4 5 6 7 8 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 9 SCL (slave output) SDA (master output) Data 1 SDA (slave output) [4] [4] Data 2 A A RDRF IRIC Interrupt request generation ICDRS Data 1 ICDRR Data 1 User processing Interrupt request generation Data 2 Data 2 [5
TM 2 H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 18.3.6 Section 18 I C Bus Interface [Option] (This function is not available in the H8S/2695) Slave Transmit Operation In slave transmit operation, the slave device compares its own address with the slave address transmitted by the master device in the first frame (address receive frame) following detection of the start condition.
2 Section 18 I C Bus Interface [Option] (This function is not available in the H8S/2695) H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 In slave transmit mode, the slave device outputs the transmit data, while the master device outputs the receive clock and returns an acknowledge signal. The transmission procedure and operations in slave transmit mode are described below. (1) Set the ICE bit in ICCR to 1.
TM 2 H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Slave receive mode SCL (master output) 8 Section 18 I C Bus Interface [Option] (This function is not available in the H8S/2695) Slave transmit mode 9 1 2 A Bit 7 Bit 6 3 4 5 6 7 8 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 9 1 2 Bit 7 Bit 6 SDA (slave output) SDA (slave output) SDA (slave output) R/W Data 1 [2] Data 2 A TDRE [4] Interrupt request generation IRIC ICDRT Interrupt request generation Interrupt
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 2 Section 18 I C Bus Interface [Option] (This function is not available in the H8S/2695) 18.3.7 IRIC Setting Timing and SCL Control The interrupt request flag (IRIC) is set at different times depending on the WAIT bit in ICMR, the FS bit in SAR, and the FSX bit in SARX. If the TDRE or RDRF internal flag is set to 1, SCL is automatically held low after one frame has been transferred; this timing is synchronized with the internal clock.
TM 2 H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 18.3.8 Section 18 I C Bus Interface [Option] (This function is not available in the H8S/2695) Operation Using the DTC* 2 The I C bus format provides for selection of the slave device and transfer direction by means of the slave address and the R/W bit, confirmation of reception with the acknowledge bit, indication of the last frame, and so on.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 2 Section 18 I C Bus Interface [Option] (This function is not available in the H8S/2695) 18.3.9 Noise Canceler The logic levels at the SCL and SDA pins are routed through noise cancelers before being latched internally. Figure 18.20 shows a block diagram of the noise canceler circuit. The noise canceler consists of two cascaded latches and a match detector.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 2 Section 18 I C Bus Interface [Option] (This function is not available in the H8S/2695) 18.3.10 Initialization of Internal State The IIC has a function for forcible initialization of its internal state if a deadlock occurs during communication. Initialization is executed by (1) setting bits CLR3 to CLR0 in the DDCSWR register or (2) clearing the ICE bit. For details of settings for bits CLR3 to CLR0, see section 18.2.
2 Section 18 I C Bus Interface [Option] (This function is not available in the H8S/2695) H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 The value of the BBSY bit cannot be modified directly by this module clear function, but since the stop condition pin waveform is generated according to the state and release timing of the SCL and SDA pins, the BBSY bit may be cleared as a result. Similarly, state switching of other bits and flags may also have an effect.
TM 2 H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 18 I C Bus Interface [Option] (This function is not available in the H8S/2695) 2 Table 18.6 I C Bus Timing (SCL and SDA Output) Item Symbol Output Timing Unit Notes SCL output cycle time tSCLO 28 tcyc to 256 tcyc ns SCL output high pulse width tSCLHO 0.5 tSCLO ns Figure 25.33, figure 26.33 (reference) SCL output low pulse width tSCLLO 0.5 tSCLO ns SDA output bus free time tBUFO 0.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 2 Section 18 I C Bus Interface [Option] (This function is not available in the H8S/2695) Table 18.7 Permissible SCL Rise Time (tSr) Values Time Indication 2 I C Bus Specification φ = (Max.) 5 MHz tcyc IICX Indication 0 1 7.5 tcyc 17.
TM 2 H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 18 I C Bus Interface [Option] (This function is not available in the H8S/2695) 2 Table 18.8 I C Bus Timing (with Maximum Influence of tSr/tSf) Time Indication (at Maximum Transfer Rate) [ns] 2 Item tSCLHO tcyc Indication 0.5 tSCLO (–tSr) I C Bus tSr/tSf SpecifiInfluence cation φ = (Max.) (Min.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 2 Section 18 I C Bus Interface [Option] (This function is not available in the H8S/2695) • Note on ICDR Read at End of Master Reception To halt reception at the end of a receive operation in master receive mode, set the TRS bit to 1 and write 0 to BBSY and SCP in ICCR. This changes SDA from low to high when SCL is high, and generates the stop condition.
TM 2 H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 18 I C Bus Interface [Option] (This function is not available in the H8S/2695) • Notes on Start Condition Issuance for Retransmission Figure 18.22 shows the timing of start condition issuance for retransmission, and the timing for subsequently writing data to ICDR, together with the corresponding flowchart. [1] Wait for end of 1-byte transfer. IRIC= 1 ? No [1] [2] Determine whether SCL is low.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 2 Section 18 I C Bus Interface [Option] (This function is not available in the H8S/2695) • Notes on I C Bus Interface Stop Condition Instruction Issuance 2 If the rise time of the 9th SCL acknowledge exceeds the specification because the bus load capacitance is large, or if there is a slave device of the type that drives SCL low to effect a wait, issue the stop condition instruction after reading SCL and determining it to be low, as shown
TM 2 H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 18 I C Bus Interface [Option] (This function is not available in the H8S/2695) • Notes on IRIC Flag Clearance when Using Wait Function If the SCL rise time exceeds the designated duration or if the slave device is of the type that keeps SCL low and applies a wait state when the wait function is used in the master mode of 2 the I C bus interface, read SCL and clear the IRIC flag after determining that SCL has gone low, as shown
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 2 Section 18 I C Bus Interface [Option] (This function is not available in the H8S/2695) • Notes on ICDR Reads and ICCR Access in Slave Transmit Mode 2 In a transmit operation in the slave mode of the I C bus interface, do not read the ICDR register or read or write to the ICCR register during the period indicated by the shaded portion in figure 18.25.
TM 2 H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 18 I C Bus Interface [Option] (This function is not available in the H8S/2695) • Notes on TRS Bit Setting in Slave Mode From the detection of the rising edge of the 9th clock cycle or of a stop condition to when the rising edge of the next SCL pin signal is detected (the period indicated as (a) in figure 18.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 2 Section 18 I C Bus Interface [Option] (This function is not available in the H8S/2695) • Notes on ICDR Reads in Transmit Mode and ICDR Writes in Receive Mode When attempting to read ICDR in the transmit mode (TRS = 1) or write to ICDR in the receive mode (TRS = 0) under certain conditions, the SCL pin may not be held low after the completion of the transmit or receive operation and a clock may not be output to the SCL bus line before the
TM 2 H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 18 I C Bus Interface [Option] (This function is not available in the H8S/2695) • Arbitration is lost • The AL flag in ICSR is set to 1 I2C bus interface (Master transmit mode) S SLA R/W A DATA1 Transmit data match Transmit timing match Other device (Master transmit mode) S SLA R/W A Transmit data does not match DATA2 A DATA3 A Data contention I2C bus interface (Slave receive mode) S SLA R/W A • Receive add
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 2 Section 18 I C Bus Interface [Option] (This function is not available in the H8S/2695) • Notes on Wait Operation in Master Mode During master mode operation using the wait function, when the interrupt flag IRIC bit is cleared from 1 to 0 between the falling edge of the 7th clock cycle and the falling edge of the 8th clock cycle, in some cases no wait is inserted after the falling edge of the 8th clock cycle and the clock pulse of the 9th
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 19 A/D Converter Section 19 A/D Converter 19.1 Overview The H8S/2633 Group incorporates a successive approximation type 10-bit A/D converter that allows up to sixteen analog input channels to be selected. 19.1.1 Features A/D converter features are listed below.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 19 A/D Converter 19.1.2 Block Diagram Figure 19.1 shows a block diagram of the A/D converter.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 19.1.3 Section 19 A/D Converter Pin Configuration Table 19.1 summarizes the input pins used by the A/D converter. The AVCC and AVSS pins are the power supply pins for the analog block in the A/D converter. The Vref pin is the A/D conversion reference voltage pin.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 19 A/D Converter 19.1.4 Register Configuration Table 19.2 summarizes the registers of the A/D converter. Table 19.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 19 A/D Converter 19.2 Register Descriptions 19.2.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 19 A/D Converter 19.2.2 A/D Control/Status Register (ADCSR) Bit : Initial value : R/W : 7 6 5 4 3 2 1 0 ADF ADIE ADST SCAN CH3 CH2 CH1 CH0 0 0 0 0 0 0 0 0 R/(W)* R/W R/W R/W R/W R/W R/W R/W Note: * Only 0 can be written to bit 7, to clear this flag. ADCSR is an 8-bit readable/writable register that controls A/D conversion operations.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 19 A/D Converter Bit 5—A/D Start (ADST): Selects starting or stopping on A/D conversion. Holds a value of 1 during A/D conversion. The ADST bit can be set to 1 by software, a timer conversion start trigger, or the A/D external trigger input pin (ADTRG). Bit 5 ADST Description 0 • A/D conversion stopped 1 • Single mode: A/D conversion is started.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 19 A/D Converter Bits 2 to 0—Channel Select 2 to 0 (CH2 to CH0): Together with the SCAN bit, these bits select the analog input channels. Only set the input channel while conversion is stopped (ADST = 0).
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 19.2.3 Section 19 A/D Converter A/D Control Register (ADCR) Bit 7 6 5 4 3 2 1 0 TRGS1 TRGS0 — — CKS1 CKS0 — — 0 0 1 1 0 0 1 1 R/W R/W — — R/W R/W — — : Initial value : R/W : ADCR is an 8-bit readable/writable register that enables or disables external triggering of A/D conversion operations and sets the A/D conversion time.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 19 A/D Converter 19.2.4 Module Stop Control Register A (MSTPCRA) Bit : 7 6 5 4 3 2 0 1 MSTPA7 MSTPA6 MSTPA5 MSTPA4 MSTPA3 MSTPA2 MSTPA1 MSTPA0 Initial value : R/W : 0 0 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W MSTPCR is a 8-bit readable/writable register that performs module stop mode control.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 19.3 Section 19 A/D Converter Interface to Bus Master ADDRA to ADDRD are 16-bit registers, and the data bus to the bus master is 8 bits wide. Therefore, in accesses by the bus master, the upper byte is accessed directly, but the lower byte is accessed via a temporary register (TEMP). A data read from ADDR is performed as follows.
Section 19 A/D Converter 19.4 H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Operation The A/D converter operates by successive approximation with 10-bit resolution. It has two operating modes: single mode and scan mode. 19.4.1 Single Mode (SCAN = 0) Single mode is selected when A/D conversion is to be performed on a single channel only. A/D conversion is started when the ADST bit is set to 1, according to the software or external trigger input.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 19 A/D Converter Set* ADIE ADST A/D conversion starts Set* Set* Clear* Clear* ADF State of channel 0 (AN0) Idle State of channel 1 (AN1) Idle State of channel 2 (AN2) Idle State of channel 3 (AN3) Idle A/D conversion 1 Idle A/D conversion 2 Idle ADDRA ADDRB Read conversion result A/D conversion result 1 Read conversion result A/D conversion result 2 ADDRC ADDRD Note: * Vertical arrows ( ) indicate instruction
Section 19 A/D Converter 19.4.2 H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Scan Mode (SCAN = 1) Scan mode is useful for monitoring analog inputs in a group of one or more channels. When the ADST bit is set to 1 by a software, timer or external trigger input, A/D conversion starts on the first channel in the group (AN0). When two or more channels are selected, after conversion of the first channel ends, conversion of the second channel (AN1) starts immediately.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 19 A/D Converter Continuous A/D conversion execution Clear*1 Set*1 ADST Clear*1 ADF A/D conversion time State of channel 0 (AN0) Idle State of channel 1 (AN1) Idle State of channel 2 (AN2) Idle A/D conversion 1 Idle A/D conversion 2 Idle Idle A/D conversion 4 A/D conversion 5 *2 Idle A/D conversion 3 State of channel 3 (AN3) Idle Idle Transfer ADDRA A/D conversion result 4 A/D conversion result 1 ADDRB A/
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 19 A/D Converter 19.4.3 Input Sampling and A/D Conversion Time The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the analog input at a time tD after the ADST bit is set to 1, then starts conversion. Figure 19.5 shows the A/D conversion timing. Table 19.4 indicates the A/D conversion time. As indicated in figure 19.5, the A/D conversion time includes tD and the input sampling time.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 19 A/D Converter Table 19.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 19 A/D Converter φ ADTRG Internal trigger signal ADST A/D conversion Figure 19.6 External Trigger Input Timing 19.5 Interrupts The A/D converter generates an A/D conversion end interrupt (ADI) at the end of A/D conversion. ADI interrupt requests can be enabled or disabled by means of the ADIE bit in ADCSR. The DTC* and DMAC* can be activated by an ADI interrupt.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 19.6 Section 19 A/D Converter Usage Notes The following points should be noted when using the A/D converter. Setting Range of Analog Power Supply and Other Pins: (1) Analog input voltage range The voltage applied to analog input pin ANn during A/D conversion should be in the range AVSS ≤ ANn ≤ Vref. (2) Relation between AVCC, AVSS and VCC, VSS As the relationship between AVCC, AVSS and VCC, VSS, set AVSS = VSS.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 19 A/D Converter sample-and-hold circuit in the A/D converter exceeds the current input via the input impedance (Rin), an error will arise in the analog input pin voltage. Careful consideration is therefore required when deciding the circuit constants. AVCC Vref Rin* 2 *1 100 AN0 to AN15 *1 0.1 µF AVSS Notes: Values are reference values. 1. 10 µF 0.01 µF 2. Rin: Input impedance Figure 19.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 19 A/D Converter 10 kΩ AN0 to AN15 To A/D converter 20 pF Note: Values are reference values. Figure 19.8 Analog Input Pin Equivalent Circuit A/D Conversion Precision Definitions: H8S/2633 Group A/D conversion precision definitions are given below.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 19 A/D Converter Digital output Ideal A/D conversion characteristic 111 110 101 100 011 Quantization error 010 001 000 1 2 1024 1024 1022 1023 1024 1024 FS Analog input voltage Figure 19.9 A/D Conversion Precision Definitions (1) Full-scale error Digital output Ideal A/D conversion characteristic Nonlinearity error Actual A/D conversion characteristic FS Offset error Analog input voltage Figure 19.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 19 A/D Converter Permissible Signal Source Impedance: H8S/2633 Group analog input is designed so that conversion precision is guaranteed for an input signal for which the signal source impedance is 5 kΩ or less.
Section 19 A/D Converter Page 926 of 1434 H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 R01UH0166EJ0600 Rev. 6.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 20 D/A Converter (This function is not available in the H8S/2695) Section 20 D/A Converter (This function is not available in the H8S/2695) 20.1 Overview The H8S/2633 Group has an on-chip D/A converter module with four channels. 20.1.1 Features Features of the D/A converter module are listed below.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 20 D/A Converter (This function is not available in the H8S/2695) 20.1.2 Block Diagram Module data bus Bus interface Figure 20.1 shows a block diagram of the D/A converter. Internal data bus 8-bit D/A DA0 (DA2) DACR DA1 (DA3) DADR1 (DADR3) AVCC DADR0 (DADR2) Vref AVSS Control circuit Legend: DACR: D/A control register DADR0 to DADR3: D/A data register 0 to 3 Figure 20.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 20.1.3 Section 20 D/A Converter (This function is not available in the H8S/2695) Input and Output Pins Table 20.1 lists the input and output pins used by the D/A converter module. Table 20.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 20 D/A Converter (This function is not available in the H8S/2695) 20.2 Register Descriptions 20.2.1 D/A Data Registers 0 to 3 (DADR0 to DADR3) Bit : 7 6 5 4 3 2 1 0 Initial value : 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W : D/A data registers 0 to 3 (DADR0 to DADR3) are 8-bit readable/writable registers that store data to be converted.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 20 D/A Converter (This function is not available in the H8S/2695) Bit 6—D/A Output Enable 0 (DAOE0): Controls D/A conversion and analog output. Bit 6 DAOE0 Description 0 Analog output DA0 (DA2) is disabled 1 D/A conversion is enabled on channel 0. Analog output DA0 (DA2) is enabled (Initial value) Bit 5—D/A Enable (DAE): Controls D/A conversion, in combination with bits DAOE0 and DAOE1.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 20 D/A Converter (This function is not available in the H8S/2695) 20.2.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 20 D/A Converter (This function is not available in the H8S/2695) Module Stop Control Register A (MSTPCRA) Bit 2—Module Stop (MSTPA2): Specifies D/A converter (channels 0 and 1) module stop mode.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 20 D/A Converter (This function is not available in the H8S/2695) 20.3 Operation The D/A converter module has two built-in D/A converter circuits that can operate independently. D/A conversion is performed continuously whenever enabled by the D/A control register (DACR). When a new value is written in DADR0 or DADR1, conversion of the new value begins immediately.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 21 RAM Section 21 RAM 21.1 Overview The H8S/2633 and H8S/2633R have 16 kbytes of on-chip high-speed static RAM, the H8S/2632 has 12 kbytes, and the H8S/2631 and H8S/2695 have 8 kbytes. The RAM is connected to the CPU by a 16-bit data bus, enabling one-state access by the CPU to both byte data and word data. This makes it possible to perform fast word data transfer.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 21 RAM 21.1.2 Register Configuration The on-chip RAM is controlled by SYSCR. Table 21.1 shows the address and initial value of SYSCR. Table 21.1 RAM Register Name Abbreviation R/W Initial Value Address* System control register SYSCR R/W H'01 H'FDE5 Note: * Lower 16 bits of the address. 21.2 Register Descriptions 21.2.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 21.3 Section 21 RAM Operation When the RAME bit is set to 1, accesses to addresses H'FFB000 to H'FFEFBF and H'FFFFC0 to H'FFFFFF in the H8S/2633 and H8S/2633R, to addresses H'FFC000 to H'FFEFBF and H'FFFFC0 to H'FFFFFF in the H8S/2632, and to addresses H'FFD000 to H'FFEFBF and H'FFFFC0 to H'FFFFFF in the H8S/2631 and H8S/2695, are directed to the on-chip RAM. When the RAME bit is cleared to 0, the off-chip address space is accessed.
Section 21 RAM H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Page 938 of 1434 R01UH0166EJ0600 Rev. 6.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 22 ROM Section 22 ROM 22.1 Overview The H8S/2633 Group and H8S/2633R have 256 kbytes of on-chip flash memory, or 256 kbytes of on-chip mask ROM, the H8S/2632, H8S/2695 have 192 kbytes of mask ROM, and the H8S/2631 has 128 kbytes of mask ROM. The ROM is connected to the bus master via a 16-bit data bus, enabling both byte and word data to be accessed in one state.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 22 ROM Table 22.1 Register Configuration Register Name Abbreviation R/W Initial Value Address* Mode control register MDCR R/W Undefined H'FDE7 Note: * Lower 16 bits of the address. 22.2 Register Descriptions 22.2.1 Mode Control Register (MDCR) Bit: 7 6 5 4 3 2 1 0 — — — — — 1 0 0 0 0 MDS2 —* MDS1 —* MDS0 —* R/W — — — — R R R Initial value: R/W: Note: * Determined by pins MD2 to MD0.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 22 ROM Table 22.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 22 ROM Table 22.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 22.4 Flash Memory Overview 22.4.1 Features Section 22 ROM The H8S/2633 Group has 256 kbytes of on-chip flash memory. The features of the flash memory are summarized below. • Four flash memory operating modes ⎯ Program mode ⎯ Erase mode ⎯ Program-verify mode ⎯ Erase-verify mode • Programming/erase methods The flash memory is programmed 128 bytes at a time. Block erase (in single-block units) can be performed.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 22 ROM 22.4.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 22.4.3 Section 22 ROM Flash Memory Operating Modes Mode Transitions When the mode pins and the FWE pin are set in the reset state and a reset-start is executed, the microcomputer enters an operating mode as shown in figure 22.3. In user mode, flash memory can be read but not programmed or erased. The boot, user program and programmer modes are provided as modes to write and erase the flash memory.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 22 ROM 22.4.4 On-Board Programming Modes Boot Mode 1. Initial state The old program version or data remains written in the flash memory. The user should prepare the programming control program and new application program beforehand in the host. 2.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 22 ROM User Program Mode 1. Initial state The FWE assessment program that confirms that user program mode has been entered, and the program that will transfer the programming/erase control program from flash memory to on-chip RAM should be written into the flash memory by the user beforehand. The programming/erase control program should be prepared in the host or in the flash memory. 2.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 22 ROM 22.4.5 Flash Memory Emulation in RAM Emulation should be performed in user mode or user program mode. When the emulation block set in RAMER is accessed while the emulation function is being executed, data written in the overlap RAM is read. SCI Flash memory RAM Emulation block Overlap RAM (emulation is performed on data written in RAM) Application program Execution state Figure 22.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 22 ROM SCI RAM Flash memory Programming data Overlap RAM (programming data) Application program Programming control program execution state Figure 22.5 Writing Overlap RAM Data in User Program Mode 22.4.6 Differences between Boot Mode and User Program Mode Table 22.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 22 ROM 22.4.7 Block Configuration The flash memory is divided into three 64 kbytes blocks, one 32 kbytes block, and eight 4 kbytes blocks. Address H'00000 4 kbytes × 8 32 kbytes 256 kbytes 64 kbytes 64 kbytes 64 kbytes Address H'3FFFF Figure 22.6 Flash Memory Block Configuration 22.4.8 Pin Configuration The flash memory is controlled by means of the pins shown in table 22.5. Table 22.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 22.4.9 Section 22 ROM Register Configuration The registers used to control the on-chip flash memory when enabled are shown in table 22.6. In order to access these registers, the FLSHE bit in SCRX must be set to 1 (except for RAMER and SCRX). Table 22.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 22 ROM 22.5 Register Descriptions 22.5.1 Flash Memory Control Register 1 (FLMCR1) Bit: Initial value: R/W: 7 6 5 4 3 2 1 0 FWE —* SWE1 ESU1 PSU1 EV1 PV1 E1 P1 0 0 0 0 0 0 0 R R/W R/W R/W R/W R/W R/W R/W Note: * Determined by the state of the FWE pin. FLMCR1 is an 8-bit register used for flash memory operating mode control.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 22 ROM Bit 6—Software Write Enable Bit 1 (SWE1): This bit selects write and erase valid/invalid of the flash memory. Set it when setting bits 5 to 0, bits 7 to 0 of EBR1, and bits 3 to 0 of EBR2. Bit 6 SWE1 Description 0 Writes disabled 1 Writes enabled (Initial value) [Setting condition] When FWE = 1 Bit 5—Erase Setup Bit 1 (ESU1): Prepares for a transition to erase mode.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 22 ROM Bit 3—Erase-Verify 1 (EV1): Selects erase-verify mode transition or clearing. Do not set the SWE1, ESU1, PSU1, PV1, E1, or P1 bit at the same time. Bit 3 EV1 Description 0 Erase-verify mode cleared 1 Transition to erase-verify mode (Initial value) [Setting condition] When FWE = 1 and SWE1 = 1 Bit 2—Program-Verify 1 (PV1): Selects program-verify mode transition or clearing.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 22 ROM Bit 0—Program 1 (P1): Selects program mode transition or clearing. Do not set the SWE1, PSU1, ESU1, EV1, PV1, or E1 bit at the same time. Bit 0 P1 Description 0 Program mode cleared 1 Transition to program mode [Setting condition] When FWE = 1, SWE1 = 1, and PSU1 = 1 22.5.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 22 ROM Bits 6 to 0—Reserved: These bits always read 0. 22.5.3 Erase Block Register 1 (EBR1) Bit: Initial value: R/W: 7 6 5 4 3 2 1 0 EB7 EB6 EB5 EB4 EB3 EB2 EB1 EB0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W EBR1 is an 8-bit register that specifies the flash memory erase area block by block.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 22.5.4 Section 22 ROM Erase Block Register 2 (EBR2) Bit: 7 6 5 4 3 2 1 0 — — — — EB11 EB10 EB9 EB8 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Initial value: R/W: EBR2 is an 8-bit register that specifies the flash memory erase area block by block. EBR2 is initialized to H'00 by a power-on reset, in hardware standby mode and software standby mode, when a low level is input to the FWE pin.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 22 ROM 22.5.5 RAM Emulation Register (RAMER) Bit: 7 6 5 4 3 2 1 0 — — — — RAMS RAM2 RAM1 RAM0 Initial value: 0 0 0 0 0 0 0 0 R/W: R R R/W R/W R/W R/W R/W R/W RAMER specifies the area of flash memory to be overlapped with part of RAM when emulating real-time flash memory programming. RAMER initialized to H'00 by a power-on reset and in hardware standby mode.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 22 ROM Bits 2 to 0—Flash Memory Area Selection: These bits are used together with bit 3 to select the flash memory area to be overlapped with RAM. (See table 22.8.) Table 22.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 22 ROM 22.5.6 Flash Memory Power Control Register (FLPWCR) Bit: Initial value: R/W: 7 6 5 4 3 2 1 0 PDWND — — — — — — — 0 0 0 0 0 0 0 0 R/W R R R R R R R FLPWCR enables or disables a transition to the flash memory power-down mode when the LSI switches to subactive mode.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 22 ROM 2 2 Bit 4—I C Master Enable (IICE): Controls access to the I C bus interface data registers and control registers (ICCR, ICSR, ICDR/SARX, and ICMR/SAR). For details of the control, see section 18.2.7, Serial Control Register X (SCRX). Bit 3—Flash Memory Control Register Enable (FLSHE): Controls CPU access to the flash memory control registers (FLMCR1, FLMCR2, EBR1, and EBR2).
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 22 ROM 22.6.1 Boot Mode When boot mode is used, the flash memory programming control program must be prepared in the host beforehand. The SCI channel to be used is set to asynchronous mode.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 22 ROM Start Set pins to boot mode and execute reset-start Host transfers data (H'00) continuously at prescribed bit rate H8S/2633 measures low period of H'00 data transmitted by host H8S/2633 calculates bit rate and sets value in bit rate register After bit rate adjustment, H8S/2633 transmits one H'00 data byte to host to indicate end of adjustment Host confirms normal reception of bit rate adjustment end indication (H'00), and
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 22 ROM Automatic SCI Bit Rate Adjustment Start bit D0 D1 D2 D3 D4 D5 D6 D7 Stop bit High period (1 or more bits) Low period (9 bits) measured (H'00 data) Figure 22.9 SCI Bit Rate Adjustment Operation When boot mode is initiated, the H8S/2633 Group measures the low period of the asynchronous SCI communication data (H'00) transmitted continuously from the host.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 22 ROM On-Chip RAM Area Divisions in Boot Mode: In boot mode, the RAM area is divided into an area used by the boot program and an area to which the programming control program is transferred via the SCI, as shown in figure 22.10. The boot program area cannot be used until the execution state in boot mode switches to the programming control program transferred from the host.
Section 22 ROM H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 • Before branching to the programming control program (RAM area H'FFC000), the chip terminates transmit and receive operations by the on-chip SCI (channel 2) (by clearing the RE and TE bits in SCR to 0), but the adjusted bit rate value remains set in BRR. The transmit data output pin, TxD2, goes to the high-level output state (PA1DDR = 1, PA1DR = 1).
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 22 ROM To select user program mode, select a mode that enables the on-chip flash memory (mode 6 or 7), and apply a high level to the FWE pin. In this mode, on-chip supporting modules other than flash memory operate as they normally would in modes 6 and 7.
Section 22 ROM 22.7 H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Programming/Erasing Flash Memory A software method, using the CPU, is employed to program and erase flash memory in the onboard programming modes. There are four flash memory operating modes: program mode, erase mode, program-verify mode, and erase-verify mode. Transitions to these modes are made by setting the PSU1, ESU1, P1, E1, PV1, and EV1 bits in FLMCR1 for addresses H'000000 to H'03FFFF.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 22 ROM *3 E1 = 1 Erase setup state Erase mode E1 = 0 Normal mode FWE = 1 ESU1 = 1 *1 ESU1 = 0 FWE = 0 EV1 = 1 *2 On-board SWE1 = 1 Software programming mode programming Software programming enable disable state SWE1 = 0 state Erase-verify mode EV1 = 0 PSU1 = 1 *4 P1 = 1 PSU1 = 0 Program setup state Program mode P1 = 0 PV1 = 1 PV1 = 0 Program-verify mode Notes: In order to perform a normal read of flash memory, SWE
Section 22 ROM H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 The wait times after bits are set or cleared in the flash memory control register 1 (FLMCR1) and the maximum number of programming operations (N1 + N2) are shown in table 25-13 and 26-13 in section 25.6 and 26.6, Flash Memory Characteristics.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 22 ROM Notes on Program/Program-Verify Procedure 1. In order to perform 128-byte-unit programming, the lower 8 bits of the write start address must be H'00 or H'80. 2. When performing continuous writing of 128-byte data to flash memory, byte-unit transfer should be used. 128-byte data transfer is necessary even when writing fewer than 128 bytes of data. Write H'FF data to the extra addresses. 3. Verify data is read in word units.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 22 ROM Reprogram Data Computation Table (D) Result of Verify-Read (X) after Write Pulse Result of Operation Comments Application (V) 0 0 1 Programming completed: reprogramming processing not to be executed 0 1 0 Programming incomplete: reprogramming processing to be executed 1 0 1 ⎯ 1 1 1 Still in erased state: no action Legend: (D): Source data of bits on which programming is executed (X): Source data of bits on
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 22 ROM Start of programming Programming must be executed in the erased state. Do not perform additional programming on addresses that have already been programmed.
Section 22 ROM 22.7.3 H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Erase Mode When erasing flash memory, the single-block erase/erase-verify flowchart shown in figure 22.14 should be followed. To erase flash memory contents, make a 1-bit setting for the flash memory area to be erased in erase block register 1 and 2 (EBR1, EBR2) at least (x) µs after setting the SWE1 bit to 1 in FLMCR1. Next, the watchdog timer (WDT) is set to prevent overerasing due to program runaway, etc.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 22 ROM Start Perform erasing in block units *1 Set SWE1 bit in FLMCR1 Wait (× 0) μs *5 n=1 Set EBR1 and 2 *3 *4 Enable WDT Set ESU1 bit in FLMCR1 Wait (y) μs *5 Start erase Set E1 bit in FLMCR1 Wait (z) ms *5 Clear E1 bit in FLMCR1 Halt erase Wait (α) μs *5 Clear ESU1 bit in FLMCR1 Wait (β) μs *5 Disable WDT n←n+1 Set EV1 bit in FLMCR1 Wait (γ) μs *5 Set block start address to verify address H'FF dummy write
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 22 ROM 22.8 Protection There are three kinds of flash memory program/erase protection: hardware protection, software protection, and error protection. 22.8.1 Hardware Protection Hardware protection refers to a state in which programming/erasing of flash memory is forcibly disabled or aborted.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 22.8.2 Section 22 ROM Software Protection Software protection can be implemented by setting the SWE1 bit in FLMCR1, erase block register 1 (EBR1), erase block register 2 (EBR2), and the RAMS bit in the RAM emulation register (RAMER). When software protection is in effect, setting the P1 or E1 bit in flash memory control register 1 (FLMCR1), does not cause a transition to program mode or erase mode. (See table 22.12.) Table 22.
Section 22 ROM 22.8.3 H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Error Protection In error protection, an error is detected when H8S/2633 Group runaway occurs during flash memory programming/erasing, or operation is not performed in accordance with the program/erase algorithm, and the program/erase operation is aborted. Aborting the program/erase operation prevents damage to the flash memory due to overprogramming or overerasing.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 22 ROM Figure 22.15 shows the flash memory state transition diagram.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 22 ROM 22.9 Flash Memory Emulation in RAM Making a setting in the RAM emulation register (RAMER) enables part of RAM to be overlapped onto the flash memory area so that data to be written to flash memory can be emulated in RAM in real time. After the RAMER setting has been made, accesses cannot be made from the flash memory area or the RAM area overlapping flash memory.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 22 ROM This area can be accessed from both the RAM area and flash memory area H'00000 EB0 H'01000 EB1 H'02000 EB2 H'03000 EB3 H'04000 EB4 H'05000 EB5 H'06000 EB6 H'07000 EB7 H'08000 H'FFD000 H'FFDFFF Flash memory EB8 to EB11 On-chip RAM H'FFEFBF H'3FFFF Figure 22.17 Example of RAM Overlap Operation Example in which Flash Memory Block Area EB0 is Overlapped 1.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 22 ROM 22.10 Interrupt Handling when Programming/Erasing Flash Memory All interrupts, including NMI interrupt is disabled when flash memory is being programmed or erased (when the P1 or E1 bit is set in FLMCR1), and while the boot program is executing in boot 1 mode* , to give priority to the program or erase operation. There are three reasons for this: 1.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 22 ROM Table 22.13 shows the pin settings for programmer mode. Table 22.13 Programmer Mode Pin Settings Pin Names Settings Mode pins: MD2, MD1, MD0 Low level input to MD2, MD1, and MD0.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 22 ROM Addresses in MCU mode Addresses in programmer mode H'000000 H'00000 On-chip ROM space 256 kbytes H'03FFFF H'3FFFF Figure 22.18 On-Chip ROM Memory Map Page 984 of 1434 R01UH0166EJ0600 Rev. 6.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 22.12 Section 22 ROM Flash Memory and Power-Down States In addition to its normal operating state, the flash memory has power-down states in which power consumption is reduced by halting part or all of the internal power supply circuitry. There are three flash memory operating states: (1) Normal operating mode: The flash memory can be read and written to.
Section 22 ROM 22.13 H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Flash Memory Programming and Erasing Precautions Precautions concerning the use of on-board programming mode, the RAM emulation function, and programmer mode are summarized below. Use the specified voltages and timing for programming and erasing: Applied voltages in excess of the rating can permanently damage the device.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 22 ROM Do not apply a constant high level to the FWE pin: Apply a high level to the FWE pin only when programming or erasing flash memory. A system configuration in which a high level is constantly applied to the FWE pin should be avoided. Also, while a high level is applied to the FWE pin, the watchdog timer should be activated to prevent overprogramming or overerasing due to program runaway, etc.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 22 ROM Wait time: x Programming/ erasing possible Wait time: 100 μs φ Min 0 μs tOSC1 VCC tMDS*3 FWE Min 0 μs MD2 to MD0*1 tMDS*3 RES SWE1 set SWE1 cleared SWE1 bit Period during which flash memory access is prohibited (x: Wait time after setting SWE1 bit)*2 Period during which flash memory can be programmed (Execution of program in flash memory prohibited, and data reads other than verify operations prohibited) Notes: 1.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 22 ROM Wait time: x Programming/ erasing possible Wait time: 100 μs φ Min 0 μs tOSC1 VCC FWE MD2 to MD0*1 tMDS*3 RES SWE1 set SWE1 cleared SWE1 bit Period during which flash memory access is prohibited (x: Wait time after setting SWE1 bit)*2 Period during which flash memory can be programmed (Execution of program in flash memory prohibited, and data reads other than verify operations prohibited) Notes: 1.
Wait time: 100 μs Wait time: x Programming/erasing possible Wait time: x Programming/erasing possible Wait time: 100 μs Wait time: 100 μs Wait time: x Programming/erasing possible Section 22 ROM Wait time: x Programming/erasing possible Wait time: 100 μs H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 φ tOSC1 VCC Min 0 μs FWE tMDS tMDS*2 MD2 to MD0 tMDS tRESW RES SWE1 bit SWE1 set Mode change*1 SWE1 cleared Boot mode Mode User change*1 mode User program mode User mode Use
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 22.14 Section 22 ROM Note on Switching from F-ZTAT Version to Mask ROM Version The mask ROM version does not have the internal registers for flash memory control that are provided in the F-ZTAT version. Table 22.16 lists the registers that are present in the F-ZTAT version but not in the mask ROM version. If a register listed in table 22.16 is read in the mask ROM version, an undefined value will be returned.
Section 22 ROM H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Page 992 of 1434 R01UH0166EJ0600 Rev. 6.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 23A Clock Pulse Generator (H8S/2633, H8S/2632, H8S/2631, H8S/2633F) Section 23A Clock Pulse Generator (H8S/2633, H8S/2632, H8S/2631, H8S/2633F) 23A.1 Overview The H8S/2633 Group has a built-in clock pulse generator (CPG) that generates the system clock (φ), the bus master clock, and internal clocks.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 23A Clock Pulse Generator (H8S/2633, H8S/2632, H8S/2631, H8S/2633F) 23A.1.2 Register Configuration The clock pulse generator is controlled by SCKCR and LPWRCR. Table 23A.1 shows the register configuration. Table 23A.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 23A Clock Pulse Generator (H8S/2633, H8S/2632, H8S/2631, H8S/2633F) Bits 6 to 4—Reserved: These bits are always read as 0 and cannot be modified. Bit 3—Frequency Multiplication Factor Switching Mode Select (STCS): Selects the operation when the PLL circuit frequency multiplication factor is changed.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 23A Clock Pulse Generator (H8S/2633, H8S/2632, H8S/2631, H8S/2633F) Bits 1 and 0—Frequency Multiplication Factor (STC1, STC0): The STC bits specify the frequency multiplication factor of the PLL circuit.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 23A Clock Pulse Generator (H8S/2633, H8S/2632, H8S/2631, H8S/2633F) Table 23A.2 Damping Resistance Value Frequency (MHz) 2 4 8 12 16 20 25 Rd (Ω) 500 200 0 0 0 0 1k Crystal Resonator: Figure 23A.3 shows the equivalent circuit of the crystal resonator. Use a crystal resonator that has the characteristics shown in table 23A.3. CL L Rs XTAL EXTAL C0 AT-cut parallel-resonance type Figure 23A.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 23A Clock Pulse Generator (H8S/2633, H8S/2632, H8S/2631, H8S/2633F) External circuitry such as that shown below is recommended around the PLL. R1: 3 kΩ C1: 470 pF PLLCAP Rp: 200 Ω PLLVCC CPB: 0.1 μF* PLLVSS PVCC VCC CB: 0.1 μF* CB: 0.1 μF* VSS (Values are recommended values.) Note: * CB and CPB are laminated ceramic capacitors. Figure 23A.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 23A Clock Pulse Generator (H8S/2633, H8S/2632, H8S/2631, H8S/2633F) 23A.3.2 External Clock Input Circuit Configuration: An external clock signal can be input as shown in the examples in figure 23A.6. If the XTAL pin is left open, make sure that stray capacitance is no more than 10 pF. In example (b), make sure that the external clock is held high in standby mode.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 23A Clock Pulse Generator (H8S/2633, H8S/2632, H8S/2631, H8S/2633F) External Clock: Table 23A.4 and figure 23A.7 show the input conditions for the external clock. Table 23A.4 External Clock Input Conditions VCC = 3.0 V to 3.6 V, PVCC = 3.0 V to 5.5 V VCC = 3.0 V to 3.6 V, PVCC = 5.0 V ±10% Min Max Min Max Unit Test Conditions External clock input low tEXL pulse width 20 — 15 — ns Figure 23A.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 23A Clock Pulse Generator (H8S/2633, H8S/2632, H8S/2631, H8S/2633F) 23A.4 PLL Circuit The PLL circuit has the function of multiplying the frequency of the clock from the oscillator by a factor of 1, 2, or 4. The multiplication factor is set with the STC bits in LPWRCR. The phase of the rising edge of the internal clock is controlled so as to match that at the EXTAL pin.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 23A Clock Pulse Generator (H8S/2633, H8S/2632, H8S/2631, H8S/2633F) 23A.6 Bus Master Clock Selection Circuit The bus master clock selection circuit selects the system clock (φ) or one of the medium-speed clocks (φ/2, φ/4, φ/8, φ/16, and φ/32) to be supplied to the bus master, according to the settings of the SCK2 to SCK0 bits in SCKCR. 23A.7 Subclock Oscillator (1) Connecting 32.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 23A Clock Pulse Generator (H8S/2633, H8S/2632, H8S/2631, H8S/2633F) (2) Handling pins when subclock not required If no subclock is required, connect the OSC1 pin to Vcc and leave OSC2 open, as shown in figure 23A.10. VCC OSC1 OSC2 Open Figure 23A.10 Pin Handling When Subclock Not Required 23A.
Section 23A Clock Pulse Generator (H8S/2633, H8S/2632, H8S/2631, H8S/2633F) Page 1004 of 1434 H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 R01UH0166EJ0600 Rev. 6.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 23B Clock Pulse Generator (H8S/2633R, H8S/2695) Section 23B Clock Pulse Generator (H8S/2633R, H8S/2695) 23B.1 Overview The H8S/2633R has a built-in clock pulse generator (CPG) that generates the system clock (φ), the bus master clock, and internal clocks.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 23B Clock Pulse Generator (H8S/2633R, H8S/2695) 23B.1.1 Block Diagram Figure 23B.1 shows a block diagram of the clock pulse generator.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 23B Clock Pulse Generator (H8S/2633R, H8S/2695) 23B.2 Register Descriptions 23B.2.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 23B Clock Pulse Generator (H8S/2633R, H8S/2695) Bits 2 to 0—System Clock Select 2 to 0 (SCK2 to SCK0): These bits select the bus master clock. Bit 2 Bit 1 Bit 0 SCK2 SCK1 SCK0 Description 0 0 0 Bus master is in high-speed mode 1 Medium-speed clock is φ/2 0 Medium-speed clock is φ/4 1 Medium-speed clock is φ/8 0 Medium-speed clock is φ/16 1 Medium-speed clock is φ/32 — — 1 1 0 1 (Initial value) 23B.2.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 23B Clock Pulse Generator (H8S/2633R, H8S/2695) Bits 1 and 0—Frequency Multiplication Factor (STC1, STC0): The STC bits specify the frequency multiplication factor of the PLL circuit.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 23B Clock Pulse Generator (H8S/2633R, H8S/2695) Table 23B.2 Damping Resistance Value Frequency (MHz) 2 4 8 12 16 20 25 Rd (Ω) 500 200 0 0 0 0 1k Crystal Resonator: Figure 23B.3 shows the equivalent circuit of the crystal resonator. Use a crystal resonator that has the characteristics shown in table 23B.3. CL L Rs XTAL EXTAL C0 AT-cut parallel-resonance type Figure 23B.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 23B Clock Pulse Generator (H8S/2633R, H8S/2695) External circuitry such as that shown below is recommended around the PLL. R1: 3 kΩ C1: 470 pF PLLCAP PLLVSS PVCC CB: 0.1 μF* VSS (Values are recommended values.) Note: * CB and CPB are laminated ceramic capacitors. Figure 23B.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 23B Clock Pulse Generator (H8S/2633R, H8S/2695) 23B.3.2 External Clock Input Circuit Configuration: An external clock signal can be input as shown in the examples in figure 23B.6. If the XTAL pin is left open, make sure that stray capacitance is no more than 10 pF. In example (b), make sure that the external clock is held high in standby mode.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 23B Clock Pulse Generator (H8S/2633R, H8S/2695) External Clock Table 23B.4 and figure 23B.7 show the input conditions for the external clock. Table 23B.4 External Clock Input Conditions PVCC = 5.0 V ±10% Item Symbol Min Max Unit Test Conditions External clock input low pulse width tEXL 15 — ns Figure 23B.
Section 23B Clock Pulse Generator (H8S/2633R, H8S/2695) H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 23B.4 PLL Circuit The PLL circuit has the function of multiplying the frequency of the clock from the oscillator by a factor of 1, 2, or 4. The multiplication factor is set with the STC bits in LPWRCR. The phase of the rising edge of the internal clock is controlled so as to match that at the EXTAL pin.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 23B Clock Pulse Generator (H8S/2633R, H8S/2695) 23B.6 Bus Master Clock Selection Circuit The bus master clock selection circuit selects the system clock (φ) or one of the medium-speed clocks (φ/2, φ/4, φ/8, φ/16, and φ/32) to be supplied to the bus master, according to the settings of the SCK2 to SCK0 bits in SCKCR. 23B.7 Subclock Oscillator (This function is not available in the H8S/2695) (1) Connecting 32.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 23B Clock Pulse Generator (H8S/2633R, H8S/2695) (2) Handling pins when subclock not required If no subclock is required, connect the OSC1 pin to Vss and leave OSC2 open, as shown in figure 23B.10. OSC1 OSC2 Open Figure 23B.10 Pin Handling When Subclock Not Required Note: The H8S/2695 is not equipped with a subclock function. The pins corresponding to OSC1 and OSC2 are NC pins. 23B.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 24 Power-Down Modes Section 24 Power-Down Modes 24.1 Overview In addition to the normal program execution state, the H8S/2633 Group has eight power-down modes in which operation of the CPU and oscillator is halted and power dissipation is reduced. Low-power operation can be achieved by individually controlling the CPU, on-chip supporting modules, and so on.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 24 Power-Down Modes Table 24.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 24 Power-Down Modes Program-halted state STBY pin = Low Reset state STBY pin = High RES pin = Low Hardware standby mode RES pin = High Program execution state SSBY= 0, LSON= 0 SLEEP command High-speed mode (main clock) Sleep mode (main clock) Any interrupt SCK2 to SCK0= 0 SCK2 to SCK0 ≠ 0 Medium-speed mode (main clock) SLEEP command External interrupt*3 SLEEP command SSBY = 1, PSS = 1 DTON = 1, LSON = 1 Clock switching
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 24 Power-Down Modes Program-halted state STBY pin = Low Reset state STBY pin = High RES pin = Low Hardware standby mode RES pin = High Program execution state SSBY = 0 SLEEP command High-speed mode (main clock) Sleep mode (main clock) Any interrupt SCK2 to SCK0 = 0 SCK2 to SCK0 ≠ 0 Medium-speed mode (main clock) SLEEP command External interrupt* : Transition after exception processing SSBY = 1, PSS = 0 Software standby mo
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 24 Power-Down Modes Table 24.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 24 Power-Down Modes 24.1.1 Register Configuration Power-down modes are controlled by the SBYCR, SCKCR, LPWRCR, TCSR (WDT1*), and MSTPCR registers. Table 24.3 summarizes these registers. Note: * WDT1 is not available in the H8S/2695. Table 24.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 24 Power-Down Modes 24.2 Register Descriptions 24.2.1 Standby Control Register (SBYCR) Bit : Initial value : R/W : 7 6 5 4 3 2 1 0 SSBY STS2 STS1 STS0 OPE — — — 0 0 0 0 1 0 0 0 R/W R/W R/W R/W R/W — — — SBYCR is an 8-bit readable/writable register that performs power-down mode control. SBYCR is initialized to H'08 by a reset and in hardware standby mode.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 24 Power-Down Modes Bits 6 to 4—Standby Timer Select 2 to 0 (STS2 to STS0): These bits select the MCU wait time for clock stabilization when shifting to high-speed mode or medium-speed mode by using a specific interrupt or command to cancel software standby mode, watch mode*, or subactive mode*. With a crystal oscillator (table 24.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 24.2.2 Section 24 Power-Down Modes System Clock Control Register (SCKCR) Bit 7 6 5 4 3 2 1 0 PSTOP — — — STCS SCK2 SCK1 SCK0 : 0 0 0 0 0 0 0 0 R/W — — — R/W R/W R/W R/W Initial value : R/W : SCKCR is an 8-bit readable/writable register that performs φ clock output control, selection of operation when the PLL circuit frequency multiplication factor is changed, and medium-speed mode control.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 24 Power-Down Modes Bits 2 to 0—System Clock Select (SCK2 to SCK0): These bits select the bus master clock in high-speed mode, medium-speed mode, and subactive mode*. Set SCK2 to SCK0 all to 0 when shifting to operation in watch mode or subactive mode*. Note: * This function is not available in the H8S/2695.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 24 Power-Down Modes to 2. For details of other bits, see section 23A.2.2 and 23B.2.2, Low-Power Control Register (LPWRCR). Bit 7—Direct Transition ON Flag (DTON): When shifting to low power dissipation mode by executing the SLEEP instruction, this bit specifies whether or not to make a direct transition between high-speed mode or medium-speed mode and the subactive modes*.
Section 24 Power-Down Modes H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Bit 6—Low-Speed ON Flag (LSON): When shifting to low power dissipation mode by executing the SLEEP instruction, this bit specifies the operating mode, in combination with other control bits. This bit also controls whether to shift to high-speed mode or subactive mode* when watch mode* is cancelled. Note: * This function is not available in the H8S/2695.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 24 Power-Down Modes Bit 3—Oscillation Circuit Feedback Resistance Control Bit (RFCUT): This bit turns the internal feedback resistance of the main clock oscillation circuit ON/OFF. Bit 3 RFCUT Description 0 When the main clock is oscillating, sets the feedback resistance ON.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 24 Power-Down Modes WDT1 TCSR Bit 4 1 PSS* Description 0 • • TCNT counts the divided clock from the φ-based prescaler (PSM). When the SLEEP instruction is executed in high-speed mode or medium-speed mode, operation shifts to sleep mode or software standby mode. (Initial value) 1 • • TCNT counts the divided clock from the φsubclock-based prescaler (PSS).
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 24 Power-Down Modes MSTPCR is initialized to H'3FFFFF by a reset and in hardware standby mode. It is not initialized in software standby mode. MSTPCRA/MSTPCRB/MSTPCRC Bits 7 to 0—Module Stop (MSTPA7 to MSTPA0, MSTPB7 to MSTPB0, MSTPC7 to MSTPC0): These bits specify module stop mode. See table 24.4 for the method of selecting the on-chip peripheral functions.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 24 Power-Down Modes When the RES and MRES pins are set Low and medium-speed mode is cancelled, operation shifts to the reset state. The same applies in the case of a reset caused by overflow of the watchdog timer. When the STBY pin is driven low, a transition is made to hardware standby mode. Figure 24.2 shows the timing for transition to and clearance of medium-speed mode.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 24 Power-Down Modes (2) Exiting Sleep Mode by RES or MRES Pins Setting the RES or MRES pin level Low selects the reset state. After the stipulated reset input duration, driving the RES and MRES pins High starts the CPU performing reset exception processing. (3) Exiting Sleep Mode by STBY Pin When the STBY pin level is driven low, a transition is made to hardware standby mode. 24.5 Module Stop Mode 24.5.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 24 Power-Down Modes Table 24.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 24.5.2 Section 24 Power-Down Modes Usage Notes DMAC and DTC Module Stop (DMAC and DTC functions are not available in the H8S/2695): Depending on the operating status of the DMAC and DTC, the MSTPA7 and MSTPA6 bits may not be set to 1. Setting of the DMAC or DTC module stop mode should be carried out only when the respective module is not activated.
Section 24 Power-Down Modes 24.6.2 H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Exiting Software Standby Mode Software standby mode is cleared by an external interrupt (NMI pin, or pins IRQ0 to IRQ7), or by means of the RES pin, MRES pin or STBY pin.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 24 Power-Down Modes Table 24.5 Oscillation Stabilization Time Settings Standby STS2 STS1 STS0 Time 25 20 16 12 10 8 6 4 2 MHz MHz MHz MHz MHz MHz MHz MHz MHz Unit 0 0 1 1 0 1 0 8192 states 0.32 0.41 0.51 0.65 0.8 1.0 1.3 2.0 1 16384 states 0.65 0.82 1.0 1.3 1.6 2.0 2.7 4.1 0 32768 states 1.3 1.6 2.0 2.7 3.3 4.1 5.5 1 65536 states 2.6 3.3 4.1 5.5 6.6 0 131072 states 5.2 6.
Section 24 Power-Down Modes H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Oscillator φ NMI NMIEG SSBY NMI exception Software standby mode handling (power-down mode) NMIEG=1 SSBY=1 SLEEP instruction Oscillation stabilization time tOSC2 NMI exception handling Figure 24.3 Software Standby Mode Application Example 24.6.5 Usage Notes I/O Port Status: In software standby mode, I/O port states are retained.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 24.7 Hardware Standby Mode 24.7.1 Hardware Standby Mode Section 24 Power-Down Modes When the STBY pin is driven low, a transition is made to hardware standby mode from any mode. In hardware standby mode, all functions enter the reset state and stop operation, resulting in a significant reduction in power dissipation. As long as the prescribed voltage is supplied, on-chip RAM data is retained.
Section 24 Power-Down Modes H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Oscillator RES STBY Oscillation stabilization time Reset exception handling Figure 24.4 Hardware Standby Mode Timing 24.8 Watch Mode (This function is not available in the H8S/2695) 24.8.1 Watch Mode CPU operation makes a transition to watch mode when the SLEEP instruction is executed in highspeed mode or subactive mode with SBYCR SSBY=1, LPWRCR DTON = 0, and TCSR (WDT1) PSS = 1.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 24.8.2 Section 24 Power-Down Modes Exiting Watch Mode Watch mode is exited by any interrupt (WOVI1 interrupt, NMI pin, or IRQ0 to IRQ7), or signals at the RES, MRES, or STBY pins. (1) Exiting Watch Mode by Interrupts When an interrupt occurs, watch mode is exited and a transition is made to high-speed mode or medium-speed mode when the LPWRCR LSON bit = 0 or to subactive mode when the LSON bit = 1.
Section 24 Power-Down Modes H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 24.9 Subsleep Mode (This function is not available in the H8S/2695) 24.9.1 Subsleep Mode When the SLEEP instruction is executed with the SBYCR SSBY bit = 0, LPWRCR LSON bit = 1, and TCSR (WDT1) PSS bit = 1, CPU operation shifts to subsleep mode. In subsleep mode, the CPU is stopped. Supporting modules other than TMR0 to TMR3, WDT0, and WDT1 are also stopped.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 24.10 Section 24 Power-Down Modes Subactive Mode (This function is not available in the H8S/2695) 24.10.1 Subactive Mode When the SLEEP instruction is executed in high-speed mode with the SBYCR SSBY bit = 1, LPWRCR DTON bit = 1, LSON bit = 1, and TCSR (WDT1) PSS bit = 1, CPU operation shifts to subactive mode. When an interrupt occurs in watch mode, and if the LSON bit of LPWRCR is 1, a transition is made to subactive mode.
Section 24 Power-Down Modes 24.11 H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Direct Transitions (This function is not available in the H8S/2695) 24.11.1 Overview of Direct Transitions There are three modes, high-speed, medium-speed, and subactive, in which the CPU executes programs. When a direct transition is made, there is no interruption of program execution when shifting between high-speed and subactive modes.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 24.12 Section 24 Power-Down Modes φ Clock Output Disabling Function Output of the φ clock can be controlled by means of the PSTOP bit in SCKCR, and DDR for the corresponding port. When the PSTOP bit is set to 1, the φ clock stops at the end of the bus cycle, and φ output goes high. φ clock output is enabled when the PSTOP bit is cleared to 0.
Section 24 Power-Down Modes 24.13 H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Usage Notes (1) DMAC/DTC activation and subactive mode/watch mode transition When a transition is made to subactive mode or watch mode, make a module stop setting for the DMAC/DTC (write 1 to the corresponding bit in MSTPCR), then read 1 from that bit for confirmation, before making the mode transition.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 25 Electrical Characteristics (H8S/2633, H8S/2632, H8S/2631, H8S/2633F) Section 25 Electrical Characteristics (H8S/2633, H8S/2632, H8S/2631, H8S/2633F) 25.1 Absolute Maximum Ratings Table 25.1 lists the absolute maximum ratings. Unless specified otherwise, PVCC refers to both PVCC1 and PVCC2. Table 25.1 Absolute Maximum Ratings Item Symbol Value Unit VCC –0.3 to +4.3 V PVCC1,2 –0.3 to +7.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 25 Electrical Characteristics (H8S/2633, H8S/2632, H8S/2631, H8S/2633F) 25.2 DC Characteristics Table 25.2 lists the DC characteristics. Table 25.3 lists the permissible output currents. Table 25.2 DC Characteristics (1) Conditions: VCC = PLLVCC = 3.0 V to 3.6 V, PVCC = 4.5 V to 5.5 V, AVCC = 4.5 V to 5.5 V, Vref = 4.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Item Input leakage current Three-state leakage current (off state) Current 2 dissipation* Typ Max Unit | Iin | — — 1.0 µA STBY, NMI, MD2 to MD0 — — 1.0 µA Ports 4, 9 — — 1.0 µA Vin = 0.5 V to AVCC – 0.5 V ⏐ITSI⏐ — — 1.0 µA Vin = 0.5 V to PVCC – 0.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 25 Electrical Characteristics (H8S/2633, H8S/2632, H8S/2631, H8S/2633F) Item Port power supply 2 current* Analog power supply current Reference power supply current Test Conditions Symbol Min Typ Max Unit PICC — 17 PVCC = 5.0 V 25 mA Subclock operation — — 50 µA Standby — 0.01 5.0 Ta ≤ 50 °C Watch mode — — 20 50 °C < Ta During A/D and AlCC D/A conversion — 0.6 2.0 mA Idle — 0.01 5.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 25 Electrical Characteristics (H8S/2633, H8S/2632, H8S/2631, H8S/2633F) Table 25.2 DC Characteristics (2) 7 Conditions: VCC = PLLVCC = 3.0 V to 3.6 V, PVCC = 3.0 V to 5.5 V, AVCC = 3.6 V to 5.5 V* , 8 Vref = 3.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 25 Electrical Characteristics (H8S/2633, H8S/2632, H8S/2631, H8S/2633F) Item Three-state leakage current (off state) Typ Max Unit ⏐ITSI⏐ — — 1.0 µA Vin = 0.5 V to PVCC – 0.5 V –IP 25 — 300 µA Vin = 0 V Cin — — 30 pF Vin = 0 V NMI — — 30 pF f = 1 MHz All input pins except RES and NMI — — 15 pF Ta = 25°C — 40 60 mA VCC = 3.3 V VCC = 3.6 V f = 16 MHz Sleep mode — 35 45 mA VCC = 3.3 V VCC = 3.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Item Port power supply 3 current* Analog power supply current Section 25 Electrical Characteristics (H8S/2633, H8S/2632, H8S/2631, H8S/2633F) Typ PICC — 16 10 PVCC = 5.0 V mA Subclock operation — — 50 µA Standby — 0.01 5.0 Ta ≤ 50°C Watch mode — — 20 50 °C < Ta — 0.6 2.0 mA — 0.01 5.0 µA — 4.0 5.0 mA — 0.01 5.0 µA 2.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 25 Electrical Characteristics (H8S/2633, H8S/2632, H8S/2631, H8S/2633F) Table 25.3 Permissible Output Currents 1 Conditions A: VCC = PLLVCC = 3.0 V to 3.6 V, PVCC = 3.0 V to 5.5 V, AVCC = 3.6 V to 5.5 V* , 2 Vref = 3.6 V to AVCC* , VSS = AVSS = PLLVSS = 0 V, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications) Conditions B: VCC = PLLVCC = 3.0 V to 3.6 V, PVCC = 4.5 V to 5.5 V, AVCC = 4.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 25 Electrical Characteristics (H8S/2633, H8S/2632, H8S/2631, H8S/2633F) Table 25.4 Bus Drive Characteristics 1 Conditions A: VCC = PLLVCC = 3.0 V to 3.6 V, PVCC = 3.0 V to 5.5 V, AVCC = 3.6 V to 5.5 V* , 2 Vref = 3.6 V to AVCC* , VSS = AVSS = PLLVSS = 0 V, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications) Conditions B: VCC = PLLVCC = 3.0 V to 3.6 V, PVCC = 4.5 V to 5.5 V, AVCC = 4.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 25 Electrical Characteristics (H8S/2633, H8S/2632, H8S/2631, H8S/2633F) 25.3 AC Characteristics Figure 25.1 show, the test conditions for the AC characteristics. 5V RL LSI output pin C RH C = 50 pF: Ports 10 to 13, 70 to 73, A to G (In case of expansion bus control signal output pin setting) C = 30 pF: All ports except ports 10 to 13, 70 to 73, A to G RL = 2.4 kΩ RH = 12 kΩ Input/output timing measurement levels • Low level: 0.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 25.3.1 Section 25 Electrical Characteristics (H8S/2633, H8S/2632, H8S/2631, H8S/2633F) Clock Timing Table 25.5 lists the clock timing Table 25.5 Clock Timing Condition A: VCC = PLLVCC = 3.0 V to 3.6 V, PVCC = 3.0 V to 5.5 V, AVCC = 3.6 V to 5.5 V* , 2 Vref = 3.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 25 Electrical Characteristics (H8S/2633, H8S/2632, H8S/2631, H8S/2633F) tcyc tCH tCf φ tCL tCr Figure 25.2 System Clock Timing EXTAL tDEXT tDEXT VCC STBY tOSC1 tOSC1 RES φ Figure 25.3 Oscillator Settling Timing Page 1058 of 1434 R01UH0166EJ0600 Rev. 6.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 25.3.2 Section 25 Electrical Characteristics (H8S/2633, H8S/2632, H8S/2631, H8S/2633F) Control Signal Timing Table 25.6 lists the control signal timing. Table 25.6 Control Signal Timing Condition A: 1 VCC = PLLVCC = 3.0 V to 3.6 V, PVCC = 3.0 V to 5.5 V, AVCC = 3.6 V to 5.5 V* , 2 Vref = 3.6 V to AVCC* , VSS = AVSS = PLLVSS = 0 V, φ = 32.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 25 Electrical Characteristics (H8S/2633, H8S/2632, H8S/2631, H8S/2633F) φ tRESS tRESS tMRESS tMRESS RES tRESW MRES tMRESW Figure 25.4 Reset Input Timing φ tNMIS tNMIH NMI tNMIW IRQ tIRQW tIRQS tIRQH IRQ Edge input tIRQS IRQ Level input Figure 25.5 Interrupt Input Timing Page 1060 of 1434 R01UH0166EJ0600 Rev. 6.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 25.3.3 Section 25 Electrical Characteristics (H8S/2633, H8S/2632, H8S/2631, H8S/2633F) Bus Timing Table 25.7 lists the bus timing. Table 25.7 Bus Timing Condition A: 1 VCC = PLLVCC = 3.0 V to 3.6 V, PVCC = 3.0 V to 5.5 V, AVCC = 3.6 V to 5.5 V* , 2 Vref = 3.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 25 Electrical Characteristics (H8S/2633, H8S/2632, H8S/2631, H8S/2633F) Condition A Condition B Item Symbol Min Max Min Max Unit WR delay time 1 tWRD1 — 30 — 18 ns WR delay time 2 tWRD2 — 30 — 18 ns WR pulse width 1 tWSW1 1.0 × tcyc – 30 — 1.0 × tcyc – 15 — ns WR pulse width 2 tWSW2 1.5 × tcyc – 30 — 1.5 × tcyc – 15 — ns Write data delay time tWDD — 30 — 22 ns Write data setup time tWDS 0.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 25 Electrical Characteristics (H8S/2633, H8S/2632, H8S/2631, H8S/2633F) T1 T2 φ tAD A23 to A0 tCSD1 tAH tAS CS7 to CS0 tASD tASD AS tRSD1 RD (read) tAS tRSD2 tACC2 tACC3 tRDS tRDH D15 to D0 (read) tWRD2 tWRD2 WR (write) tAS tWDD tWSW1 tAH tWDH D15 to D0 (write) Figure 25.6 Basic Bus Timing (Two-State Access) R01UH0166EJ0600 Rev. 6.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 25 Electrical Characteristics (H8S/2633, H8S/2632, H8S/2631, H8S/2633F) T1 T2 T3 φ tAD A23 to A0 tCSD1 tAS tAH CS7 to CS0 tASD tASD AS tRSD1 RD (read) tACC4 tAS tRSD2 tRDS tRDH tACC5 D15 to D0 (read) tWRD1 tWRD2 WR (write) tAH tWDD tWDS tWSW2 tWDH D15 to D0 (write) Figure 25.7 Basic Bus Timing (Three-State Access) Page 1064 of 1434 R01UH0166EJ0600 Rev. 6.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 T1 Section 25 Electrical Characteristics (H8S/2633, H8S/2632, H8S/2631, H8S/2633F) T2 TW T3 φ A23 to A0 CS7 to CS0 AS RD (read) D15 to D0 (read) WR (write) D15 to D0 (write) tWTS tWTH tWTS tWTH WAIT Figure 25.8 Basic Bus Timing (Three-State Access with One Wait State) R01UH0166EJ0600 Rev. 6.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 25 Electrical Characteristics (H8S/2633, H8S/2632, H8S/2631, H8S/2633F) T1 T2 or T3 T1 T2 φ tAD A23 to A0 tAH tAS CS7 to CS0 tASD tASD AS tRSD2 RD (read) tACC3 tRDS tRDH D15 to D0 (read) Figure 25.9 Burst ROM Access Timing (Two-State Access) Page 1066 of 1434 R01UH0166EJ0600 Rev. 6.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 25 Electrical Characteristics (H8S/2633, H8S/2632, H8S/2631, H8S/2633F) T1 T2 or T3 T1 φ tAD A23 to A0 CS7 to CS0 AS tRSD2 RD (read) tACC1 tRDS tRDH D15 to D0 (read) Figure 25.10 Burst ROM Access Timing (One-State Access) R01UH0166EJ0600 Rev. 6.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 25 Electrical Characteristics (H8S/2633, H8S/2632, H8S/2631, H8S/2633F) Tp Tr TC1 TC2 φ tAD tAD A23 to A0 tPCH tAS tAH tCSD tACC4 CS5 to CS2 (RAS) tCSD2 tCASD1 tACC1 tCASD1 tCP1 CAL, LCAS (RCTS=0) CAL to LCAS (When RCTS is set to 1) (read) tCASD2 tACC2 tOED2 tACC2 tCASD1 tCP2 tOED1 OE (When OES is set to 1) (read) tACC3 tRDS tRDH D15 to D0 (read) tWRD1 tWRD1 HWR, LWR (write) tWDD tWCS tWDS tWCH tWDH D1
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 TRp Section 25 Electrical Characteristics (H8S/2633, H8S/2632, H8S/2631, H8S/2633F) TRr TRC1 TRC2 φ tCSD2 CS5 to CS2 (RAS) tCSD1 tCSR tCASD1 tCASD1 CAS, LCAS Figure 25.12 DRAM CBR Refresh Timing TRp TRr TRC TRC φ tCSD2 CS5 to CS2 (RAS) tCSD2 tCSR tCASD1 tCASD1 CAS, LCAS Figure 25.13 DRAM Self-Refresh Timing R01UH0166EJ0600 Rev. 6.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 25 Electrical Characteristics (H8S/2633, H8S/2632, H8S/2631, H8S/2633F) φ tBRQS tBRQS BREQ tBACD tBACD BACK tBZD tBZD A23 to A0 CS7 to CS0, AS, RD, HWR, LWR Figure 25.14 External Bus Release Timing φ tBRQOD tBRQOD BREQO Figure 25.15 External Bus Request Output Timing Page 1070 of 1434 R01UH0166EJ0600 Rev. 6.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 25.3.4 Section 25 Electrical Characteristics (H8S/2633, H8S/2632, H8S/2631, H8S/2633F) DMAC Timing Table 25.8 shows the DMAC timing. Table 25.8 DMAC Timing Condition A: 1 VCC = PLLVCC = 3.0 V to 3.6 V, PVCC = 3.0 V to 5.5 V, AVCC = 3.6 V to 5.5 V* , 2 Vref = 3.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 25 Electrical Characteristics (H8S/2633, H8S/2632, H8S/2631, H8S/2633F) T1 T2 φ A23 to A0 CS7 to CS0 AS RD (read) D15 to D0 (read) HWR to LWR D15 to D0 (write) tDACD1 tDACD2 DACK0, DACK1 Figure 25.16 DMAC Single Address Transfer Timing / Two-State Access Page 1072 of 1434 R01UH0166EJ0600 Rev. 6.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 25 Electrical Characteristics (H8S/2633, H8S/2632, H8S/2631, H8S/2633F) T1 T2 T3 φ A23 to A0 CS7 to CS0 AS RD (read) D15 to D0 (read) HWR to LWR D15 to D0 (write) tDACD1 tDACD2 DACK0, DACK1 Figure 25.17 DMAC Single Address Transfer Timing / Three-State Access T1 T2 or T3 φ tTED tTED TEND0, TEND1 Figure 25.18 DMAC TEND Output Timing R01UH0166EJ0600 Rev. 6.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 25 Electrical Characteristics (H8S/2633, H8S/2632, H8S/2631, H8S/2633F) φ tDRQS tDRQH DREQ0, DREQ1 Figure 25.19 DMAC DREQ Input Timing Page 1074 of 1434 R01UH0166EJ0600 Rev. 6.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 25.3.5 Section 25 Electrical Characteristics (H8S/2633, H8S/2632, H8S/2631, H8S/2633F) Timing of On-Chip Supporting Modules Table 25.9 lists the timing of on-chip supporting modules. Table 25.9 Timing of On-Chip Supporting Modules Condition A: VCC = PLLVCC = 3.0 V to 3.6 V, PVCC = 3.0 V to 5.5 V, AVCC = 3.6 V to 5.5 V* , 2 3 Vref = 3.6 V to AVCC* , VSS = AVSS = PLLVSS = 0 V, φ = 32.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 25 Electrical Characteristics (H8S/2633, H8S/2632, H8S/2631, H8S/2633F) Condition A Item TMR Symbol Condition B Min Max Min Max Unit Test Conditions Timer output delay tTMOD time — 60 — 40 ns Figure 25.24 Timer reset input setup time tTMRS 40 — 25 — ns Figure 25.26 Timer clock input setup time tTMCS 40 — 25 — ns Figure 25.25 Timer clock pulse width Single edge tTMCWH 1.5 — 1.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 25 Electrical Characteristics (H8S/2633, H8S/2632, H8S/2631, H8S/2633F) T1 T2 φ tPRS tPRH Ports 1, 3, 4, 7, 9, A to G (read) tPWD Ports 1, 3, 7, A to G (write) Figure 25.20 I/O Port Input/Output Timing φ tPOD PO 15 to 8 Figure 25.21 PPG Output Timing φ tTOCD Output compare output* tTICS Input capture input* Note: * TIOCA0 to TIOCA5, TIOCB0 to TIOCB5, TIOCC0, TIOCC3, TIOCD0, TIOCD3 Figure 25.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 25 Electrical Characteristics (H8S/2633, H8S/2632, H8S/2631, H8S/2633F) φ tTCKS tTCKS TCLKA to TCLKD tTCKWL tTCKWH Figure 25.23 TPU Clock Input Timing φ tTMOD TMO0, TMO1 TMO2, TMO3 Figure 25.24 8-bit Timer Output Timing φ tTMCS tTMCS TMCI01, TMCI23 tTMCWL tTMCWH Figure 25.25 8-bit Timer Clock Input Timing φ tTMRS TMRI01, TMRI23 Figure 25.26 8-bit Timer Reset Input Timing Page 1078 of 1434 R01UH0166EJ0600 Rev. 6.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 25 Electrical Characteristics (H8S/2633, H8S/2632, H8S/2631, H8S/2633F) φ tWOVD tWOVD WDTOVF Figure 25.27 WDT0 Output Timing φ tBUZD tBUZD BUZZ Figure 25.28 WDT1 Output Timing φ tPWOD PWM3 to PWM0 Figure 25.29 PWM Output Timing tSCKW tSCKr tSCKf SCK0 to SCK4 tScyc Figure 25.30 SCK Clock Input Timing R01UH0166EJ0600 Rev. 6.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 25 Electrical Characteristics (H8S/2633, H8S/2632, H8S/2631, H8S/2633F) SCK0 to SCK4 tTXD TxD0 to TxD4 (transit data) tRXS tRXH RxD0 to RxD4 (receive data) Figure 25.31 SCI Input/Output Timing (Clock Synchronous Mode) φ tTRGS ADTRG Figure 25.32 A/D Converter External Trigger Input Timing Page 1080 of 1434 R01UH0166EJ0600 Rev. 6.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 25 Electrical Characteristics (H8S/2633, H8S/2632, H8S/2631, H8S/2633F) 2 Table 25.10 I C Bus Timing Condition A: VCC = PLLVCC = 3.0 V to 3.6 V, PVCC = 3.0 V to 5.5 V, AVCC = 3.6 V to 5.5 V* , 3 Vref = 3.6 V to AVCC* , VSS = AVSS = PLLVSS = 0 V, φ = 5 MHz to maximum operating frequency, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications) Condition B: VCC = PLLVCC = 3.0 V to 3.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 25 Electrical Characteristics (H8S/2633, H8S/2632, H8S/2631, H8S/2633F) VIH SDA0 to SDA1 VIL tBUF tSTAH SCL0 to SCL1 P* tSCLH tSTAS S* tSf tSCLL tSP tSTOS Sr* tSr tSCL tSDAS tSDAH Note: * S, P, and Sr indicate the following conditions. S: Start condition P: Stop condition Sr: Retransmission start condition 2 Figure 25.33 I C Bus Interface Input/Output Timing (Option) Page 1082 of 1434 R01UH0166EJ0600 Rev. 6.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 25.4 Section 25 Electrical Characteristics (H8S/2633, H8S/2632, H8S/2631, H8S/2633F) A/D Conversion Characteristics Table 25.11 lists the A/D conversion characteristics. Table 25.11 A/D Conversion Characteristics Condition A: VCC = PLLVCC = 3.0 V to 3.6 V, PVCC = 3.0 V to 5.5 V, AVCC = 3.6 V to 5.5 V* , 2 Vref = 3.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 25 Electrical Characteristics (H8S/2633, H8S/2632, H8S/2631, H8S/2633F) 25.5 D/A Conversion Characteristics Table 25.12 shows the D/A conversion characteristics. Table 25.12 D/A Conversion Characteristics 1 Condition A: VCC = PLLVCC = 3.0 V to 3.6 V, PVCC = 3.0 V to 5.5 V, AVCC = 3.6 V to 5.5 V* , 2 Vref = 3.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 25.6 Section 25 Electrical Characteristics (H8S/2633, H8S/2632, H8S/2631, H8S/2633F) Flash Memory Characteristics Table 25.13 Flash Memory Characteristics Conditions: VCC = PLLVCC = 3.0 V to 3.6 V, PVCC = 4.5 V to 5.5 V, AVCC = 4.5 V to 5.
Section 25 Electrical Characteristics (H8S/2633, H8S/2632, H8S/2631, H8S/2633F) H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 2. Programming time per 128 bytes. (Indicates the total time during which the P1 bit is set in flash memory control register 1 (FLMCR1). Does not include the program-verify time.) 3. Time to erase one block. (Indicates the time during which the E1 bit is set in FLMCR1. Does not include the erase-verify time.) 4.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 26 Electrical Characteristics (H8S/2633R) Section 26 Electrical Characteristics (H8S/2633R) 26.1 Absolute Maximum Ratings Table 26.1 lists the absolute maximum ratings. Unless specified otherwise, PVCC refers to both PVCC1 and PVCC2. Table 26.1 Absolute Maximum Ratings Item Symbol Value Unit Power supply voltage PVCC1,2 –0.3 to +7.0 V Input voltage (XTAL, EXTAL) Vin –0.3 to PVCC +0.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 26 Electrical Characteristics (H8S/2633R) 26.2 DC Characteristics Table 26.2 lists the DC characteristics. Table 26.3 lists the permissible output currents. Table 26.2 DC Characteristics Conditions: PVCC = 4.5 V to 5.5 V, AVCC = 4.5 V to 5.5 V, Vref = 4.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Item Input leakage current Three-state leakage current (off state) Current 2 dissipation* Typ Max Unit | Iin | — — 1.0 µA STBY, NMI, MD2 to MD0 — — 1.0 µA Ports 4, 9 — — 1.0 µA Vin = 0.5 V to AVCC – 0.5 V ⏐ITSI⏐ — — 1.0 µA Vin = 0.5 V to PVCC – 0.5 V –IP 50 — 300 µA Vin = 0 V Cin — — 30 pF Vin = 0 V RES, FWE Ports 1, 3, 7, A to G RES Vin = 0.5 V to PVCC – 0.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 26 Electrical Characteristics (H8S/2633R) Item Analog power supply current Reference power supply current Symbol Min Typ Max Unit Test Conditions AVCC = 5.0 V During A/D and AlCC D/A conversion — 0.6 2.0 mA Idle — 0.1 5.0 µA During A/D and AlCC D/A conversion — 4.0 5.0 mA Idle — 0.1 5.0 µA 2.0 — — V 3 RAM standby voltage* VRAM Vref = 5.0 V Notes: 1.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 26 Electrical Characteristics (H8S/2633R) Table 26.3 Permissible Output Currents Conditions: PVCC = 4.5 V to 5.5 V, AVCC = 4.5 V to 5.5 V, Vref = 4.5 V to AVCC, VSS = AVSS = PLLVSS = 0 V, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications) Item Symbol Min Typ Max Unit Permissible output low current (per pin) All output pins PVCC = 4.5 V to 5.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 26 Electrical Characteristics (H8S/2633R) Table 26.4 Bus Drive Characteristics Conditions: PVCC = 4.5 V to 5.5 V, AVCC = 4.5 V to 5.5 V, Vref = 4.5 V to AVCC, VSS = AVSS = PLLVSS = 0 V, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications) Applicable Pins: SCL1-0, SDA1-0 Item Symbol Min Typ Max Unit V Test Conditions PVCC × 0.3 — — — — PVCC × 0.7 VT+ - VT- 0.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 26.3 Section 26 Electrical Characteristics (H8S/2633R) AC Characteristics Figure 26.1 show, the test conditions for the AC characteristics. 5V RL LSI output pin C RH C = 50 pF: Ports 10 to 13, 70 to 73, A to G (In case of expansion bus control signal output pin setting) C = 30 pF: All ports except ports 10 to 13, 70 to 73, A to G RL = 2.4 kΩ RH = 12 kΩ Input/output timing measurement levels • Low level: 0.8 V • High level: 2.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 26 Electrical Characteristics (H8S/2633R) 26.3.1 Clock Timing Table 26.5 lists the clock timing Table 26.5 Clock Timing Conditions: PVCC = 4.5 V to 5.5 V, AVCC = 4.5 V to 5.5 V, Vref = 4.5 V to AVCC, VSS = AVSS = PLLVSS = 0 V, φ = 32.768 kHz, 2 to 28 MHz*, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications) 28MHz Item Symbol Min Max Unit Test Conditions Clock cycle time tcyc 35.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 26 Electrical Characteristics (H8S/2633R) tcyc tCH tCf φ tCL tCr Figure 26.2 System Clock Timing EXTAL tDEXT tDEXT VCC STBY tOSC1 tOSC1 RES φ Figure 26.3 Oscillator Settling Timing R01UH0166EJ0600 Rev. 6.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 26 Electrical Characteristics (H8S/2633R) 26.3.2 Control Signal Timing Table 26.6 lists the control signal timing. Table 26.6 Control Signal Timing Conditions: PVCC = 4.5 V to 5.5 V, AVCC = 4.5 V to 5.5 V, Vref = 4.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 26 Electrical Characteristics (H8S/2633R) φ tRESS tRESS tMRESS tMRESS RES tRESW MRES tMRESW Figure 26.4 Reset Input Timing φ tNMIS tNMIH NMI tNMIW IRQ tIRQW tIRQS tIRQH IRQ Edge input tIRQS IRQ Level input Figure 26.5 Interrupt Input Timing R01UH0166EJ0600 Rev. 6.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 26 Electrical Characteristics (H8S/2633R) 26.3.3 Bus Timing Table 26.7 lists the bus timing. Table 26.7 Bus Timing Conditions: PVCC = 4.5 V to 5.5 V, AVCC = 4.5 V to 5.5 V, Vref = 4.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 26 Electrical Characteristics (H8S/2633R) Item Symbol Min Max Unit Test Conditions RAS precharge time tPCH 1.5 × tcyc – 13 — ns CAS precharge time 1 tCP1 1.0 × tcyc – 8 — ns Figure 26.11 to figure 26.13 CAS precharge time 2 tCP2 0.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 26 Electrical Characteristics (H8S/2633R) T1 T2 φ tAD A23 to A0 tCSD1 tAH tAS CS7 to CS0 tASD tASD AS tRSD1 RD (read) tAS tRSD2 tACC2 tACC3 tRDS tRDH D15 to D0 (read) tWRD2 tWRD2 WR (write) tAS tWDD tWSW1 tAH tWDH D15 to D0 (write) Figure 26.6 Basic Bus Timing (Two-State Access) Page 1100 of 1434 R01UH0166EJ0600 Rev. 6.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 26 Electrical Characteristics (H8S/2633R) T1 T2 T3 φ tAD A23 to A0 tCSD1 tAS tAH CS7 to CS0 tASD tASD AS tRSD1 RD (read) tACC4 tAS tRSD2 tRDS tRDH tACC5 D15 to D0 (read) tWRD1 tWRD2 WR (write) tAH tWDD tWDS tWSW2 tWDH D15 to D0 (write) Figure 26.7 Basic Bus Timing (Three-State Access) R01UH0166EJ0600 Rev. 6.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 26 Electrical Characteristics (H8S/2633R) T1 T2 TW T3 φ A23 to A0 CS7 to CS0 AS RD (read) D15 to D0 (read) WR (write) D15 to D0 (write) tWTS tWTH tWTS tWTH WAIT Figure 26.8 Basic Bus Timing (Three-State Access with One Wait State) Page 1102 of 1434 R01UH0166EJ0600 Rev. 6.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 T1 Section 26 Electrical Characteristics (H8S/2633R) T2 or T3 T1 T2 φ tAD A23 to A0 tAH tAS CS7 to CS0 tASD tASD AS tRSD2 RD (read) tACC3 tRDS tRDH D15 to D0 (read) Figure 26.9 Burst ROM Access Timing (Two-State Access) R01UH0166EJ0600 Rev. 6.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 26 Electrical Characteristics (H8S/2633R) T1 T2 or T3 T1 φ tAD A23 to A0 CS7 to CS0 AS tRSD2 RD (read) tACC1 tRDS tRDH D15 to D0 (read) Figure 26.10 Burst ROM Access Timing (One-State Access) Page 1104 of 1434 R01UH0166EJ0600 Rev. 6.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 26 Electrical Characteristics (H8S/2633R) Tp Tr TC1 TC2 ø tAD tAD A23 to A0 tPCH tAS tAH tCSD tACC4 CS5 to CS2 (RAS) tCSD2 tCASD1 tACC1 tCASD1 tCP1 CAL, LCAS (RCTS=0) CAL to LCAS (When RCTS is set to 1) (read) tCASD2 tACC2 tOED2 tACC2 tCASD1 tCP2 tOED1 OE (When OES is set to 1) (read) tACC3 tRDS tRDH D15 to D0 (read) tWRD1 tWRD1 HWR, LWR (write) tWDD tWCS tWDS tWCH tWDH D15 to D0 (write) Figure 26.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 26 Electrical Characteristics (H8S/2633R) TRp TRr TRC1 TRC2 φ tCSD2 CS5 to CS2 (RAS) tCSD1 tCSR tCASD1 tCASD1 CAS, LCAS Figure 26.12 DRAM CBR Refresh Timing TRp TRr TRC TRC φ tCSD2 CS5 to CS2 (RAS) tCSD2 tCSR tCASD1 tCASD1 CAS, LCAS Figure 26.13 DRAM Self-Refresh Timing Page 1106 of 1434 R01UH0166EJ0600 Rev. 6.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 26 Electrical Characteristics (H8S/2633R) φ tBRQS tBRQS BREQ tBACD tBACD BACK tBZD tBZD A23 to A0 CS7 to CS0, AS, RD, HWR, LWR Figure 26.14 External Bus Release Timing φ tBRQOD tBRQOD BREQO Figure 26.15 External Bus Request Output Timing R01UH0166EJ0600 Rev. 6.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 26 Electrical Characteristics (H8S/2633R) 26.3.4 DMAC Timing Table 26.8 shows the DMAC timing. Table 26.8 DMAC Timing Conditions: PVCC = 4.5 V to 5.5 V, AVCC = 4.5 V to 5.5 V, Vref = 4.5 V to AVCC, VSS = AVSS = PLLVSS = 0 V, φ = 2 to 28 MHz, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications) Item Symbol Min Max Unit Test Conditions DREQ setup time tDRQS 25 — ns Figure 26.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 26 Electrical Characteristics (H8S/2633R) T1 T2 φ A23 to A0 CS7 to CS0 AS RD (read) D15 to D0 (read) HWR to LWR D15 to D0 (write) tDACD1 tDACD2 DACK0, DACK1 Figure 26.16 DMAC Single Address Transfer Timing / Two-State Access R01UH0166EJ0600 Rev. 6.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 26 Electrical Characteristics (H8S/2633R) T1 T2 T3 φ A23 to A0 CS7 to CS0 AS RD (read) D15 to D0 (read) HWR to LWR D15 to D0 (write) tDACD1 tDACD2 DACK0, DACK1 Figure 26.17 DMAC Single Address Transfer Timing / Three-State Access T1 T2 or T3 φ tTED tTED TEND0, TEND1 Figure 26.18 DMAC TEND Output Timing Page 1110 of 1434 R01UH0166EJ0600 Rev. 6.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 26 Electrical Characteristics (H8S/2633R) φ tDRQS tDRQH DREQ0, DREQ1 Figure 26.19 DMAC DREQ Input Timing R01UH0166EJ0600 Rev. 6.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 26 Electrical Characteristics (H8S/2633R) 26.3.5 Timing of On-Chip Supporting Modules Table 26.9 lists the timing of on-chip supporting modules. Table 26.9 Timing of On-Chip Supporting Modules Conditions: PVCC = 4.5 V to 5.5 V, AVCC = 4.5 V to 5.5 V, Vref = 4.5 V to AVCC, VSS = AVSS = PLLVSS = 0 V, φ = 32.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 26 Electrical Characteristics (H8S/2633R) Item SCI Symbol Min Max Unit Test Conditions Transmit data delay time tTXD — 40 ns Figure 26.31 Receive data setup time (synchronous) tRXS 40 — Receive data hold time (synchronous) tRXH 40 — tTRGS 40 — ns Figure 26.32 A/D Trigger input setup time converter Note: * Only available I/O port, TMR, WDT0, and WDT1.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 26 Electrical Characteristics (H8S/2633R) φ tTOCD Output compare output* tTICS Input capture input* Note: * TIOCA0 to TIOCA5, TIOCB0 to TIOCB5, TIOCC0, TIOCC3, TIOCD0, TIOCD3 Figure 26.22 TPU Input/Output Timing φ tTCKS tTCKS TCLKA to TCLKD tTCKWL tTCKWH Figure 26.23 TPU Clock Input Timing φ tTMOD TMO0, TMO1 TMO2, TMO3 Figure 26.24 8-bit Timer Output Timing Page 1114 of 1434 R01UH0166EJ0600 Rev. 6.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 26 Electrical Characteristics (H8S/2633R) φ tTMCS tTMCS TMCI01, TMCI23 tTMCWL tTMCWH Figure 26.25 8-bit Timer Clock Input Timing φ tTMRS TMRI01, TMRI23 Figure 26.26 8-bit Timer Reset Input Timing φ tWOVD tWOVD WDTOVF Figure 26.27 WDT0 Output Timing φ tBUZD tBUZD BUZZ Figure 26.28 WDT1 Output Timing R01UH0166EJ0600 Rev. 6.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 26 Electrical Characteristics (H8S/2633R) φ tPWOD PWM3 to PWM0 Figure 26.29 PWM Output Timing tSCKr tSCKW tSCKf SCK0 to SCK4 tScyc Figure 26.30 SCK Clock Input Timing SCK0 to SCK4 tTXD TxD0 to TxD4 (transit data) tRXS tRXH RxD0 to RxD4 (receive data) Figure 26.31 SCI Input/Output Timing (Clock Synchronous Mode) φ tTRGS ADTRG Figure 26.32 A/D Converter External Trigger Input Timing Page 1116 of 1434 R01UH0166EJ0600 Rev. 6.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Table 26.10 Section 26 Electrical Characteristics (H8S/2633R) 2 I C Bus Timing Conditions: PVCC = 4.5 V to 5.5 V, AVCC = 4.5 V to 5.5 V, Vref = 4.5 V to AVCC, VSS = AVSS = PLLVSS = 0 V, φ = 5 MHz to maximum operating frequency, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications) Ratings Item Symbol Min Typ Max Unit Notes SCL input cycle time tSCL 12 tcyc — — ns Figure 26.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 26 Electrical Characteristics (H8S/2633R) VIH SDA0 to SDA1 VIL tBUF tSTAH SCL0 to SCL1 P* tSCLH tSTAS S* tSf tSCLL tSP tSTOS Sr* tSr tSCL tSDAS tSDAH Note: * S, P, and Sr indicate the following conditions. S: Start condition P: Stop condition Sr: Retransmission start condition 2 Figure 26.33 I C Bus Interface Input/Output Timing (Option) Page 1118 of 1434 R01UH0166EJ0600 Rev. 6.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 26.4 Section 26 Electrical Characteristics (H8S/2633R) A/D Conversion Characteristics Table 26.11 lists the A/D conversion characteristics. Table 26.11 A/D Conversion Characteristics Conditions: PVCC = 4.5 V to 5.5 V, AVCC = 4.5 V to 5.5 V, Vref = 4.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 26 Electrical Characteristics (H8S/2633R) 26.5 D/A Conversion Characteristics Table 26.12 shows the D/A conversion characteristics. Table 26.12 D/A Conversion Characteristics Conditions: PVCC = 4.5 V to 5.5 V, AVCC = 4.5 V to 5.5 V, Vref = 4.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 26.6 Section 26 Electrical Characteristics (H8S/2633R) Flash Memory Characteristics Table 26.13 Flash Memory Characteristics Conditions: PVCC = 4.5 V to 5.5 V, AVCC = 4.5 V to 5.5 V, Vref = 4.
Section 26 Electrical Characteristics (H8S/2633R) H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 2. Programming time per 128 bytes. (Indicates the total time during which the P1 bit is set in flash memory control register 1 (FLMCR1). Does not include the program-verify time.) 3. Time to erase one block. (Indicates the time during which the E1 bit is set in FLMCR1. Does not include the erase-verify time.) 4.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 27 Electrical Characteristics (H8S/2695) Section 27 Electrical Characteristics (H8S/2695) 27.1 Absolute Maximum Ratings Table 27.1 lists the absolute maximum ratings. Unless specified otherwise, PVCC refers to both PVCC1 and PVCC2. Table 27.1 Absolute Maximum Ratings Item Symbol Value Unit Power supply voltage PVCC –0.3 to +7.0 V Input voltage (ports 4 and 9) Vin –0.3 to AVCC +0.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 27 Electrical Characteristics (H8S/2695) 27.2 DC Characteristics Table 27.2 lists the DC characteristics. Table 27.3 lists the permissible output currents. Table 27.2 DC Characteristics Conditions: PVCC = 4.5 V to 5.5 V, AVCC = 4.5 V to 5.5 V, Vref = 4.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 27 Electrical Characteristics (H8S/2695) Item Symbol Min Typ Max Unit Test Conditions MOS input Ports A to E pull-up current –IP 50 — 300 µA Vin = 0 V Cin — — 30 pF Vin = 0 V Input capacitance Current 2 dissipation* RES NMI — — 30 pF f = 1 MHz All input pins except RES and NMI — — 15 pF Ta = 25°C — 70 84 mA f = 28 MHz Sleep mode — 55 77 mA f = 28 MHz All modules stopped — 40 — mA
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 27 Electrical Characteristics (H8S/2695) Table 27.3 Permissible Output Currents Conditions: PVCC = 4.5 V to 5.5 V, AVCC = 4.5 V to 5.5 V, Vref = 4.5 V to AVCC, VSS = AVSS = PLLVSS = 0 V, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications) Item Symbol Min Typ Max Unit Permissible output low current (per pin) All output pins PVCC = 4.5 V to 5.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 27.3 Section 27 Electrical Characteristics (H8S/2695) AC Characteristics Figure 27.1 show, the test conditions for the AC characteristics. 5V RL LSI output pin C RH C = 50 pF: Ports 10 to 13, 70 to 73, A to G (In case of expansion bus control signal output pin setting) C = 30 pF: All ports except ports 10 to 13, 70 to 73, A to G RL = 2.4 kΩ RH = 12 kΩ Input/output timing measurement levels • Low level: 0.8 V • High level: 2.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 27 Electrical Characteristics (H8S/2695) 27.3.1 Clock Timing Table 27.4 lists the clock timing Table 27.4 Clock Timing Conditions: PVCC = 4.5 V to 5.5 V, AVCC = 4.5 V to 5.5 V, Vref = 4.5 V to AVCC, VSS = AVSS = 0 V, φ = 2 to 28 MHz*, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications) 28MHz Item Symbol Min Max Unit Test Conditions Clock cycle time tcyc 35.7 500 ns Figure 27.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 27 Electrical Characteristics (H8S/2695) tcyc tCH tCf φ tCL tCr Figure 27.2 System Clock Timing EXTAL tDEXT tDEXT VCC STBY tOSC1 tOSC1 RES φ Figure 27.3 Oscillator Settling Timing R01UH0166EJ0600 Rev. 6.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 27 Electrical Characteristics (H8S/2695) 27.3.2 Control Signal Timing Table 27.5 lists the control signal timing. Table 27.5 Control Signal Timing Conditions: PVCC = 4.5 V to 5.5 V, AVCC = 4.5 V to 5.5 V, Vref = 4.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 27 Electrical Characteristics (H8S/2695) φ tRESS tRESS tMRESS tMRESS RES tRESW MRES tMRESW Figure 27.4 Reset Input Timing φ tNMIS tNMIH NMI tNMIW IRQ tIRQW tIRQS tIRQH IRQ Edge input tIRQS IRQ Level input Figure 27.5 Interrupt Input Timing R01UH0166EJ0600 Rev. 6.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 27 Electrical Characteristics (H8S/2695) 27.3.3 Bus Timing Table 27.6 lists the bus timing. Table 27.6 Bus Timing Conditions: PVCC = 4.5 V to 5.5 V, AVCC = 4.5 V to 5.5 V, Vref = 4.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 27 Electrical Characteristics (H8S/2695) Item Symbol Min Max Unit Conditions WAIT setup time tWTS 25 — ns Figure 27.8 WAIT hold time tWTH 5 — ns BREQ setup time tBRQS 30 — ns BACK delay time tBACD — 15 ns Bus-floating time tBZD — 40 ns BREQO delay time tBRQOD — 25 ns R01UH0166EJ0600 Rev. 6.00 Mar 02, 2011 Figure 27.11 Figure 27.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 27 Electrical Characteristics (H8S/2695) T1 T2 φ tAD A23 to A0 tCSD1 tAH tAS CS7 to CS0 tASD tASD AS tRSD1 RD (read) tAS tRSD2 tACC2 tACC3 tRDS tRDH D15 to D0 (read) tWRD2 tWRD2 WR (write) tAS tWDD tWSW1 tAH tWDH D15 to D0 (write) Figure 27.6 Basic Bus Timing (Two-State Access) Page 1134 of 1434 R01UH0166EJ0600 Rev. 6.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 27 Electrical Characteristics (H8S/2695) T1 T2 T3 φ tAD A23 to A0 tCSD1 tAS tAH CS7 to CS0 tASD tASD AS tRSD1 RD (read) tACC4 tAS tRSD2 tRDS tRDH tACC5 D15 to D0 (read) tWRD1 tWRD2 WR (write) tAH tWDD tWDS tWSW2 tWDH D15 to D0 (write) Figure 27.7 Basic Bus Timing (Three-State Access) R01UH0166EJ0600 Rev. 6.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 27 Electrical Characteristics (H8S/2695) T1 T2 TW T3 φ A23 to A0 CS7 to CS0 AS RD (read) D15 to D0 (read) WR (write) D15 to D0 (write) tWTS tWTH tWTS tWTH WAIT Figure 27.8 Basic Bus Timing (Three-State Access with One Wait State) Page 1136 of 1434 R01UH0166EJ0600 Rev. 6.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 T1 Section 27 Electrical Characteristics (H8S/2695) T2 or T3 T1 T2 φ tAD A23 to A0 tAH tAS CS7 to CS0 tASD tASD AS tRSD2 RD (read) tACC3 tRDS tRDH D15 to D0 (read) Figure 27.9 Burst ROM Access Timing (Two-State Access) R01UH0166EJ0600 Rev. 6.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 27 Electrical Characteristics (H8S/2695) T1 T2 or T3 T1 φ tAD A23 to A0 CS7 to CS0 AS tRSD2 RD (read) tACC1 tRDS tRDH D15 to D0 (read) Figure 27.10 Burst ROM Access Timing (One-State Access) Page 1138 of 1434 R01UH0166EJ0600 Rev. 6.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 27 Electrical Characteristics (H8S/2695) φ tBRQS tBRQS BREQ tBACD tBACD BACK tBZD tBZD A23 to A0 CS7 to CS0, AS, RD, HWR, LWR Figure 27.11 External Bus Release Timing φ tBRQOD tBRQOD BREQO Figure 27.12 External Bus Request Output Timing R01UH0166EJ0600 Rev. 6.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 27 Electrical Characteristics (H8S/2695) 27.3.4 Timing of On-Chip Supporting Modules Table 27.7 lists the timing of on-chip supporting modules. Table 27.7 Timing of On-Chip Supporting Modules Conditions: PVCC = 4.5 V to 5.5 V, AVCC = 4.5 V to 5.5 V, Vref = 4.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Section 27 Electrical Characteristics (H8S/2695) T1 T2 φ tPRS tPRH Ports 1, 3, 4, 7, 9, A to G (read) tPWD Ports 1, 3, 7, A to G (write) Figure 27.13 I/O Port Input/Output Timing φ tTOCD Output compare output* tTICS Input capture input* Note: * TIOCA0 to TIOCA5, TIOCB0 to TIOCB5, TIOCC0, TIOCC3, TIOCD0, TIOCD3 Figure 27.14 TPU Input/Output Timing φ tTCKS tTCKS TCLKA to TCLKD tTCKWL tTCKWH Figure 27.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Section 27 Electrical Characteristics (H8S/2695) φ tWOVD tWOVD WDTOVF Figure 27.16 WDT0 Output Timing tSCKr tSCKW tSCKf SCK0 to SCK4 tScyc Figure 27.17 SCK Clock Input Timing SCK0 to SCK4 tTXD TxD0 to TxD4 (transit data) tRXS tRXH RxD0 to RxD4 (receive data) Figure 27.18 SCI Input/Output Timing (Clock Synchronous Mode) φ tTRGS ADTRG Figure 27.19 A/D Converter External Trigger Input Timing Page 1142 of 1434 R01UH0166EJ0600 Rev.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 27.4 Section 27 Electrical Characteristics (H8S/2695) A/D Conversion Characteristics Table 27.8 lists the A/D conversion characteristics. Table 27.8 A/D Conversion Characteristics Conditions: PVCC = 4.5 V to 5.5 V, AVCC = 4.5 V to 5.5 V, Vref = 4.
Section 27 Electrical Characteristics (H8S/2695) Page 1144 of 1434 H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 R01UH0166EJ0600 Rev. 6.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Appendix A Instruction Set Appendix A Instruction Set A.
Appendix A Instruction Set H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Condition Code Notation Symbol Changes according to the result of instruction * Undetermined (no guaranteed value) 0 Always cleared to 0 1 Always set to 1 — Not affected by execution of the instruction Page 1146 of 1434 R01UH0166EJ0600 Rev. 6.
MOV Operand Size W 4 W W MOV.W @ERs,Rd B MOV.B Rs,@aa:16 MOV.W Rs,Rd B MOV.B Rs,@aa:8 MOV.W #xx:16,Rd B MOV.B Rs,@-ERd B B MOV.B Rs,@(d:32,ERd) MOV.B Rs,@aa:32 B B B MOV.B @aa:32,Rd MOV.B Rs,@(d:16,ERd) B MOV.B @aa:16,Rd MOV.B Rs,@ERd B MOV.B @(d:32,ERs),Rd B B MOV.B @(d:16,ERs),Rd MOV.B @aa:8,Rd B MOV.B @ERs,Rd MOV.B @ERs+,Rd B B MOV.
MOV W W L 6 L L L MOV.W Rs,@aa:16 MOV.W Rs,@aa:32 MOV.L #xx:32,ERd MOV.L ERs,ERd MOV.L @ERs,ERd MOV.L @(d:16,ERs),ERd L W MOV.W Rs,@-ERd MOV.L @aa:32,ERd W MOV.W Rs,@(d:32,ERd) L W MOV.W Rs,@(d:16,ERd) L W MOV.W Rs,@ERd MOV.L @aa:16,ERd W MOV.W @aa:32,Rd MOV.L @ERs+,ERd W MOV.W @aa:16,Rd L W MOV.W @ERs+,Rd MOV.L @(d:32,ERs),ERd W MOV.W @(d:32,ERs),Rd Operand Size W #xx MOV.
R01UH0166EJ0600 Rev. 6.
L B B W 4 DAA Rd SUB.B Rs,Rd SUB.W #xx:16,Rd DAA SUB INC INC.L #2,ERd L ADDS #2,ERd L L ADDS #1,ERd INC.L #1,ERd B ADDX Rs,Rd W B 2 ADDX #xx:8,Rd W L ADD.L ERs,ERd INC.W #2,Rd L 6 ADD.L #xx:32,ERd INC.W #1,Rd W ADD.W Rs,Rd L W 4 ADD.W #xx:16,Rd B B ADD.B Rs,Rd INC.B Rd B 2 Operand Size ADD.
W W L L B B W B W DEC.L #1,ERd DEC.L #2,ERd DAS Rd MULXU.B Rs,Rd MULXU.W Rs,ERd MULXS.B Rs,Rd MULXS.W Rs,ERd DAS MULXU MULXS DEC DEC.W #2,Rd L SUBS #2,ERd DEC.W #1,Rd L SUBS #1,ERd L B SUBX Rs,Rd B B 2 SUBX #xx:8,Rd DEC.B Rd L SUB.L ERs,ERd SUBS #4,ERd SUBS SUBX L 6 SUB.L #xx:32,ERd Operand Size W #xx SUB.
EXTU NEG CMP DIVXS B W B 2 B W 4 W L 6 L B DIVXS.B Rs,Rd DIVXS.W Rs,ERd CMP.B #xx:8,Rd CMP.B Rs,Rd CMP.W #xx:16,Rd CMP.W Rs,Rd CMP.L #xx:32,ERd CMP.L ERs,ERd NEG.B Rd L W L NEG.L ERd EXTU.W Rd EXTU.L ERd W W DIVXU.W Rs,ERd NEG.W Rd B DIVXU.
@ERn ERs→MACL MACH→ERd MACL→ERd 2 2 2 L L L LDMAC ERs,MACL STMAC MACH,ERd STMAC MACL,ERd STMAC ERs→MACH 2 L LDMAC ERs,MACH LDMAC 0→MACH, MACL @ERn+2→ERn, ERm+2→ERm (signal multiplication) @ERnx@ERm+MAC→MAC ( of @ERd) @ERd-0→CCR set, (1)→ ( of ERd32) ( of ERd32)→ ( of Rd16) — 2 Operation ( of Rd16)→ CLRMAC #xx CLRMAC @(d,ERn) — 4 @–ERn/@ERn+ MAC @ERn+, @ERm+ 4 @aa MAC 2 @(d,PC) B L EXTS.
NOT XOR OR AND Operand Size B L NOT.L ERd L XOR.L ERs,ERd W L 6 XOR.L #xx:32,ERd NOT.W Rd W XOR.W Rs,Rd NOT.B Rd W 4 XOR.W #xx:16,Rd B L OR.L ERs,ERd XOR.B Rs,Rd L 6 OR.L #xx:32,ERd B 2 W OR.W Rs,Rd XOR.B #xx:8,Rd W 4 OR.W #xx:16,Rd AND.L ERs,ERd B L AND.L #xx:32,ERd B 2 L 6 AND.W Rs,Rd OR.B Rs,Rd W AND.W #xx:16,Rd OR.B #xx:8,Rd B W 4 AND.B Rs,Rd B 2 #xx AND.
SHLL SHAR SHAL B W W L L SHLL.W Rd SHLL.W #2,Rd SHLL.L ERd SHLL.L #2,ERd L SHAR.L #2,ERd SHLL.B #2,Rd L SHAR.L ERd B W SHLL.B Rd W SHAR.W #2,Rd SHAL.L #2,ERd SHAR.W Rd L L SHAL.L ERd B W SHAL.W #2,Rd B W SHAL.W Rd SHAR.B #2,Rd B SHAL.B #2,Rd SHAR.B Rd B Operand Size SHAL.
ROTXR ROTXL SHLR L L SHLR.L ERd SHLR.L #2,ERd W L L ROTXR.L ERd ROTXR.L #2,ERd W ROTXR.W Rd ROTXR.W #2,Rd B ROTXL.L #2,ERd B ROTXL.L ERd ROTXR.B #2,Rd L L ROTXL.W #2,Rd ROTXR.B Rd W W ROTXL.W Rd B W SHLR.W #2,Rd B W SHLR.W Rd ROTXL.B #2,Rd B SHLR.B #2,Rd ROTXL.B Rd B Operand Size SHLR.
R01UH0166EJ0600 Rev. 6.00 ROTR ROTL L L ROTL.W #2,Rd ROTL.L ERd ROTL.L #2,ERd B W W L L ROTR.B #2,Rd ROTR.W Rd ROTR.W #2,Rd ROTR.L ERd ROTR.L #2,ERd B W ROTL.W Rd ROTR.B Rd B W ROTL.B #2,Rd B Mnemonic Operand Size ROTL.
Page 1158 of 1434 BCLR BSET B B B B B B BSET Rn,@aa:32 BCLR #xx:3,Rd BCLR #xx:3,@ERd BCLR #xx:3,@aa:8 BCLR #xx:3,@aa:16 BCLR #xx:3,@aa:32 B B BSET Rn,@aa:16 B B BSET Rn,@aa:8 BCLR Rn,@aa:16 B BSET Rn,@ERd BCLR Rn,@aa:8 B BSET Rn,Rd B B BSET #xx:3,@aa:32 B B BSET #xx:3,@aa:16 BCLR Rn,@ERd B BSET #xx:3,@aa:8 BCLR Rn,Rd B B BSET #xx:3,@ERd Operand Size BSET #xx:3,Rd Mnemonic (5) Bit-Manipulation Instructions Rn 2 2 2 2 @ERn 4 4 4 4 @aa 6 4 8 6 4 8 6 4 8 6 4 —
R01UH0166EJ0600 Rev. 6.
BST BILD BLD BTST B B B B B BLD #xx:3,@aa:16 BLD #xx:3,@aa:32 BILD #xx:3,Rd BILD #xx:3,@ERd BILD #xx:3,@aa:8 BILD #xx:3,@aa:16 B B BLD #xx:3,@aa:8 BST #xx:3,@aa:8 B BLD #xx:3,@ERd B B BLD #xx:3,Rd B B BTST Rn,@aa:32 BST #xx:3,@ERd B BTST Rn,@aa:16 BST #xx:3,Rd B BTST Rn,@aa:8 B B BTST Rn,@ERd BILD #xx:3,@aa:32 B B BTST Rn,Rd B Operand Size BTST #xx:3,@aa:32 Mnemonic Rn 2 2 2 2 @ERn 4 4 4 4 @aa 4 8 6 4 8 6 4 8 6 4 8 — — — — — — — — — — — — — — — — — — —
R01UH0166EJ0600 Rev. 6.
Page 1162 of 1434 BIXOR BXOR BIOR BOR B B B BIXOR #xx:3,@aa:16 BIXOR #xx:3,@aa:32 B BIXOR #xx:3,@ERd BIXOR #xx:3,@aa:8 B B BIXOR #xx:3,Rd BXOR #xx:3,@aa:16 BXOR #xx:3,@aa:32 B B BXOR #xx:3,@aa:8 B B BIOR #xx:3,@aa:32 BXOR #xx:3,@ERd B BIOR #xx:3,@aa:16 BXOR #xx:3,Rd B B BIOR #xx:3,@aa:8 B BIOR #xx:3,@ERd B BOR #xx:3,@aa:32 B B BOR #xx:3,@aa:16 BIOR #xx:3,Rd B Operand Size BOR #xx:3,@aa:8 Mnemonic Rn 2 2 2 @ERn 4 4 4 @aa 8 6 4 8 6 4 8 6 4 8 6 4 — — — — — — —
R01UH0166EJ0600 Rev. 6.
Bcc Page 1164 of 1434 — — — — — — — — — — — — — — BVS d:16 BPL d:8 BPL d:16 BMI d:8 BMI d:16 BGE d:8 BGE d:16 BLT d:8 BLT d:16 BGT d:8 BGT d:16 BLE d:8 BLE d:16 Operand Size BVS d:8 Mnemonic @(d,PC) 4 2 4 2 4 2 4 2 4 2 4 2 4 2 — @@aa @aa @–ERn/@ERn+ @(d,ERn) @ERn Rn #xx Addressing Mode/ Instruction Length (Bytes) Branching Condition else next; PC←PC+d 2 3 2 3 2 3 Z∨(N⊕V)=0 — — — — — — — — — — — — Z∨(N⊕V)=1 — — — — — — — — — — — — 3 — — — — — — 2 — — — — — — 3 — — — — —
R01UH0166EJ0600 Rev. 6.
W LDC @aa:32,EXR W LDC @aa:16,EXR W W LDC @aa:16,CCR LDC @aa:32,CCR W LDC @ERs+,EXR W LDC @(d:32,ERs),CCR W W LDC @(d:16,ERs),EXR W W LDC @(d:16,ERs),CCR LDC @ERs+,CCR W LDC @ERs,EXR LDC @(d:32,ERs),EXR W LDC @ERs,CCR B 4 LDC #xx:8,EXR B B 2 LDC #xx:8,CCR LDC B — SLEEP SLEEP LDC Rs,EXR — RTE RTE LDC Rs,CCR — Operand Size TRAPA #xx:2 #xx TRAPA Mnemonic 2 Rn 2 @ERn 4 4 @(d,ERn) 10 10 6 6 @–ERn/@ERn+ 4 4 @aa 8 8 6 6 — @@aa @(d,PC) Addressing Mode/
NOP XORC ORC ANDC B 2 ORC #xx:8,CCR — B 4 ANDC #xx:8,EXR NOP B 2 ANDC #xx:8,CCR B 4 W STC EXR,@aa:32 XORC #xx:8,EXR W STC CCR,@aa:32 B 4 W STC EXR,@aa:16 B 2 W STC CCR,@aa:16 XORC #xx:8,CCR W STC EXR,@-ERd ORC #xx:8,EXR W W STC CCR,@-ERd #xx STC EXR,@(d:32,ERd) W W STC CCR,@(d:32,ERd) STC CCR,@(d:16,ERd) STC EXR,@(d:16,ERd) W W STC EXR,@ERd B W STC CCR,@ERd B STC EXR,Rd Operand Size Mnemonic Rn 2 2 @ERn 4 4 @(d,ERn) 10 10 6 6 @–ERn/@ERn+ 4 4 @aa 8 8
Page 1168 of 1434 Notes: 1. 2. 3. 4. [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] EEPMOV — EEPMOV.W @@aa @(d,PC) @aa @–ERn/@ERn+ @(d,ERn) @ERn Rn #xx Addressing Mode/ Instruction Length (Bytes) — — — — — — 4 if R4≠0 Repeat @ER5→@ER6 ER5+1→ER5 ER6+1→ER6 R4-1→R4 Until R4=0 else next; I H N Z V C — — — — — — Operation Condition Code 4 if R4L≠0 Repeat @ER5→@ER6 ER5+1→ER5 ER6+1→ER6 R4L-1→R4L Until R4L=0 else next; — 4+2n*2 4+2n*2 Advanced No.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 A.2 Appendix A Instruction Set Instruction Codes Table A.2 shows the instruction codes. R01UH0166EJ0600 Rev. 6.
Page 1170 of 1434 Bcc BAND ANDC AND ADDX ADDS ADD Instruction rs 6 F 4 0 IMM 0 erd 1 3 6 A 1 6 1 6 C E A A 0 8 1 8 6 7 0 0 0 7 7 7 6 6 4 5 4 5 W L L B B B B B B B — — — — AND.W Rs,Rd AND.L #xx:32,ERd AND.
Bcc Instruction R01UH0166EJ0600 Rev. 6.
Page 1172 of 1434 BIOR BILD BIAND BCLR Instruction B B B B B B B B BILD #xx:3,@ERd BILD #xx:3,@aa:8 BILD #xx:3,@aa:16 BILD #xx:3,@aa:32 BIOR #xx:3,Rd BIOR #xx:3,@ERd BIOR #xx:3,@aa:8 BIOR #xx:3,@aa:16 B B BILD #xx:3,Rd BIOR #xx:3,@aa:32 B B BCLR Rn,@aa:32 BIAND #xx:3,@aa:32 B BCLR Rn,@aa:16 B B BCLR Rn,@aa:8 BIAND #xx:3,@aa:16 B BCLR Rn,@ERd B B BCLR Rn,Rd B B BCLR #xx:3,@aa:32 BIAND #xx:3,@aa:8 B BCLR #xx:3,@aa:16 BIAND #xx:3,@ERd B BCLR #xx:3,@aa:8 B B BCLR #xx:3,@ERd
Mar 02, 2011 R01UH0166EJ0600 Rev. 6.
Page 1174 of 1434 BTST BST BSR BSET BOR Instruction 5 5 6 7 7 6 6 7 7 — — B B B B B B B BSR d:8 BSR d:16 BST #xx:3,Rd BST #xx:3,@ERd BST #xx:3,@aa:8 BST #xx:3,@aa:16 BST #xx:3,@aa:32 BTST #xx:3,Rd BTST #xx:3,@ERd 7 6 B BSET Rn,@aa:32 B 6 B BSET Rn,@aa:16 BTST Rn,@ERd 7 B BSET Rn,@aa:8 6 7 B BSET Rn,@ERd B 6 B BSET Rn,Rd BTST Rn,Rd 6 B BSET #xx:3,@aa:32 6 6 B BSET #xx:3,@aa:16 B 7 B BSET #xx:3,@aa:8 BTST #xx:3,@aa:32 7 B BSET #xx:3,@ERd 6 7 B BSET #xx:3,Rd B
6 6 7 7 7 6 6 0 A 1 7 1 7 1 0 1 1 1 1 1 B B B B B B B — B B W W L L B B B W W L BTST Rn,@aa:16 BTST Rn,@aa:32 Mar 02, 2011 BXOR #xx:3,Rd BXOR #xx:3,@ERd BXOR #xx:3,@aa:8 BXOR #xx:3,@aa:16 BXOR #xx:3,@aa:32 R01UH0166EJ0600 Rev. 6.00 CMP.B #xx:8,Rd CMP.B Rs,Rd CMP.W #xx:16,Rd CMP.W Rs,Rd CMP.L #xx:32,ERd CMP.L ERs,ERd DAA Rd DAS Rd DEC.B Rd DEC.W #1,Rd DEC.W #2,Rd DEC.L #1,ERd DAA DAS DEC 0 5 5 7 W B W — DIVXS.W Rs,ERd DIVXU.B Rs,Rd DIVXU.W Rs,ERd EEPMOV.W 7 0 DIVXS.B Rs,Rd — 1 L B DEC.
Page 1176 of 1434 LDC JSR JMP INC EXTU EXTS Instruction 1 rs abs IMM 4 0 B D E F 7 1 3 5 5 5 5 0 0 0 — — — — B B B JMP @@aa:8 JSR @ERn JSR @aa:24 JSR @@aa:8 LDC #xx:8,CCR LDC #xx:8,EXR LDC Rs,CCR 0 ers 0 ers 0 ers 0 0 8 D D B B 7 6 6 6 6 1 0 1 0 1 4 4 4 4 1 1 1 1 0 0 0 0 W W W W LDC @ERs+,CCR LDC @ERs+,EXR LDC @aa:16,CCR LDC @aa:16,EXR 0 4 1 0 W LDC @(d:32,ERs),CCR 4 0 ers 8 7 1 4 1 0 W LDC @(d:16,ERs),EXR 1 0 ers F 6 0 4 1 0 W LDC @(d:16,ERs),CCR 0 0 ers F
Mar 02, 2011 R01UH0166EJ0600 Rev. 6.00 F 0 6 6 7 6 2 6 6 6 6 7 6 3 6 6 7 0 6 6 7 B B B B B B B B B B B B B B B W W W W W MOV.B Rs,Rd MOV.B @ERs,Rd MOV.B @(d:16,ERs),Rd MOV.B @(d:32,ERs),Rd MOV.B @ERs+,Rd MOV.B @aa:8,Rd MOV.B @aa:16,Rd MOV.B @aa:32,Rd MOV.B Rs,@ERd MOV.B Rs,@(d:16,ERd) MOV.B Rs,@(d:32,ERd) MOV.B Rs,@-ERd MOV.B Rs,@aa:8 MOV.B Rs,@aa :16 MOV.B Rs,@aa:32 MOV.W #xx:16,Rd MOV.W Rs,Rd MOV.W @ERs,Rd MOV.W @(d:16,ERs),Rd MOV.W @(d:32,ERs),Rd 0 B 0 L — LDMAC ERs,MACL MOV.
Page 1178 of 1434 0 ers 0 erd 0 ers 0 erd 0 ers 0 erd 0 erd 0 erd 0 ers 0 2 9 F 8 D B B 6 6 7 6 6 6 rs rs 0 erd 0 0 0 0 0 0 1 erd 8 A 0 0 0 0 0 0 0 D B B A F 1 1 1 1 1 1 6 6 6 7 0 0 0 0 0 0 0 1 erd 0 ers 1 erd 0 ers 1 erd 0 ers 0 ers 0 ers 0 erd 8 A 9 F 8 D B B 6 6 7 6 6 6 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 0 Cannot be used in the H8S/2633 Group W L L L L L L L L L L L L L L B MOV.W Rs,@aa:32 MOV.L #xx:32,ERd MOV.L ERs,ERd MOV.L @ERs,ERd MOV.L @(d:16,ERs),ERd MOV.
Mar 02, 2011 R01UH0166EJ0600 Rev. 6.00 6 7 0 0 0 6 W L L B B W OR.W Rs,Rd OR.L #xx:32,ERd OR.L ERs,ERd ORC #xx:8,CCR ORC #xx:8,EXR POP.W Rn ROTL PUSH POP ORC 1 1 1 1 1 B W W L L ROTL.W Rd ROTL.W #2, Rd ROTL.L ERd ROTL.L #2, ERd 1 ROTL.B Rd ROTL.B #2, Rd 0 L B PUSH.L ERn 6 7 W OR.W #xx:16,Rd 0 1 B OR.B Rs,Rd L C B OR.B #xx:8,Rd W 1 L NOT.L ERd PUSH.W Rn 1 W NOT.W Rd POP.L ERn 1 B NOT.B Rd OR 0 — NOP 1 L NEG.L ERd NOT 1 W NEG.
Page 1180 of 1434 1 1 L SHAL.L #2, ERd 1 W SHAL.W #2, Rd L 1 SHAL.L ERd 1 B W 1 B SHAL.B Rd SHAL SHAL.W Rd 5 — RTS RTS SHAL.B #2, Rd 5 1 L ROTXR.L ERd 1 1 W ROTXR.W #2, Rd L 1 W ROTXR.W Rd — 1 B ROTXR.B #2, Rd RTE 1 ROTXR.L #2, ERd 1 L B ROTXR.B Rd 1 L ROTXL.L ERd ROTXL.L #2, ERd 1 W ROTXL.
Mar 02, 2011 R01UH0166EJ0600 Rev. 6.00 6 6 6 6 7 7 6 6 rd rd rd rd 0 erd 0 erd rd rd rd rd 0 erd 0 erd rd rd rd rd 0 erd 0 erd 0 rd rd 0 1 0 1 0 1 0 1 8 C 9 D B F 0 4 1 5 3 7 0 4 1 5 3 7 8 0 1 4 4 4 4 4 4 4 4 1 1 1 1 1 0 0 0 0 0 0 1 1 1 1 1 1 1 2 2 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 B W W STC.W EXR,@(d:16,ERd) W STC.W CCR,@(d:32,ERd) W STC.W EXR,@(d:32,ERd) W W STC.W EXR,@ERd STC.W CCR,@(d:16,ERd) W W STC.W CCR,@ERd STC.W CCR,@-ERd STC.W EXR,@-ERd 0 B STC.B CCR,Rd STC STC.
Page 1182 of 1434 L L W XOR.W #xx:16,Rd XOR.L ERs,ERd B XOR.B Rs,Rd XOR.L #xx:32,ERd B XOR.B #xx:8,Rd XOR W — TRAPA #x:2 TRAPA XOR.W Rs,Rd B TAS @ERd B L SUBS #2,ERd SUBX Rs,Rd L SUBS #1,ERd L L SUB.L ERs,ERd B L SUB.L #xx:32,ERd SUBX #xx:8,Rd W SUB.W Rs,Rd SUBS #4,ERd W SUB.W #xx:16,Rd L B STMAC MACL,ERd SUB.B Rs,Rd L L STMAC MACH,ERd L STM.L (ERn-ERn+3), @-SP W STC.W EXR,@aa:32 STM.L (ERn-ERn+2), @-SP W STC.W CCR,@aa:32 L W STC.W EXR,@aa:16 STM.
Mar 02, 2011 B B XORC #xx:8,EXR Size XORC #xx:8,CCR Mnemonic 0 0 1 5 1st byte 4 IMM 1 2nd byte 0 5 3rd byte IMM 4th byte R01UH0166EJ0600 Rev. 6.
Page 1184 of 1434 1 2 BH 3 BL XOR BSR BCS AND RTE BNE BST TRAPA BEQ ADD MOV AND MOV XOR E OR D SUBX B F SUB ADD BVS 9 Table A.3(2) MOV Table A.3(2) C Note: * Cannot be used in the H8S/2633 Group. 8 BVC MOV.B Table A.3(2) LDC 7 BIST BXOR BAND BLD BOR BIXOR BIAND BILD BIOR OR RTS BCC AND ANDC 6 CMP BTST DIVXU BLS XOR XORC 5 ADDX BCLR MULXU BHI OR ORC 4 Table A.3(2) Table A.3(2) JMP BPL Table A.3(2) Table A.3(2) A EEPMOV BMI Table A.
Mar 02, 2011 R01UH0166EJ0600 Rev. 6.00 DAS BRA MOV MOV MOV 1F 58 6A 79 7A ADD CMP CMP MOV ADD BHI BRN 2 BH Table A.3(4) AL BCC ROTXR ROTXL SHLR SHLL STC 4 LDC SUB SUB OR OR Table * A.3(4) MOVFPE BLS NOT STM 3 BL 2nd byte Note: * Cannot be used in the H8S/2633 Group. SUBS NOT 17 1B ROTXR 13 DEC ROTXL 12 1A SHLR 11 DAA 0F SHLL ADDS 0B 1 LDM AH 1st byte 10 INC 0A 0 MOV BH 01 AH AL Instruction code Table A.
Page 1186 of 1434 0 2 BSET BNOT BNOT BCLR BCLR Notes: 1. r is the register specification field. 2. aa is the absolute address specification.
Mar 02, 2011 R01UH0166EJ0600 Rev. 6.00 BSET 0 AH BNOT 1 AL 1st byte BNOT 1 0 BSET AL AH 1st byte BCLR 2 BH 3 3 6 DL 7 EH EL 5th byte 5 DH 6 DL 4th byte 7 EH EL 5th byte BOR BXOR BAND BLD BIOR BIXOR BIAND BILD BST BIST 4 CL 3rd byte CH BTST BL 5 DH 4th byte BOR BXOR BAND BLD BIOR BIXOR BIAND BILD BST BIST 4 CL 3rd byte CH BTST BL 2nd byte BCLR 2 BH 2nd byte Note: * aa is the absolute address specification.
Appendix A Instruction Set A.4 H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Number of States Required for Instruction Execution The tables in this section can be used to calculate the number of states required for instruction execution by the CPU. Table A.5 indicates the number of instruction fetch, data read/write, and other cycles occurring in each instruction. Table A.4 indicates the number of states required for each cycle.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Table A.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Appendix A Instruction Set Table A.5 Number of Cycles in Instruction Execution Branch Byte Instruction Address Stack Data Fetch Read Operation Access Word Data Access Internal Operation M N Instruction Mnemonic I ADD ADD.B #xx:8,Rd 1 ADD.B Rs,Rd 1 ADD.W #xx:16,Rd 2 ADD.W Rs,Rd 1 ADD.L #xx:32,ERd 3 ADD.L ERs,ERd 1 ADDS #1/2/4,ERd 1 ADDS ADDX AND ANDC BAND Bcc ADDX #xx:8,Rd 1 ADDX Rs,Rd 1 AND.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Appendix A Instruction Set Branch Byte Instruction Address Stack Data Fetch Read Operation Access Word Data Access Internal Operation I M N Instruction Mnemonic Bcc BPL d:8 2 BMI d:8 2 BCLR K L BGE d:8 2 BLT d:8 2 BGT d:8 2 BLE d:8 2 BRA d:16 (BT d:16) 2 1 BRN d:16 (BF d:16) 2 1 BHI d:16 2 1 BLS d:16 2 1 BCC d:16 (BHS d:16) 2 1 BCS d:16 (BLO d:16) 2 1 BNE d:16 2 1 BEQ d:16 2 1 BVC d:16 2
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Appendix A Instruction Set Instruction BIAND BILD BIOR BIST BIXOR BLD Branch Byte Instruction Address Stack Data Fetch Read Operation Access Word Data Access Internal Operation Mnemonic I M N BIAND #xx:3,Rd 1 BIAND #xx:3,@ERd 2 J K L 1 BIAND #xx:3,@aa:8 2 1 BIAND #xx:3,@aa:16 3 1 BIAND #xx:3,@aa:32 4 1 BILD #xx:3,Rd 1 BILD #xx:3,@ERd 2 1 BILD #xx:3,@aa:8 2 1 BILD #xx:3,@aa:16 3 1 BILD #xx:3,@aa:32 4
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Instruction BNOT BOR BSET BSR BST Mnemonic Branch Byte Instruction Address Stack Data Fetch Read Operation Access Word Data Access Internal Operation I M N J K L BNOT #xx:3,Rd 1 BNOT #xx:3,@ERd 2 2 BNOT #xx:3,@aa:8 2 2 BNOT #xx:3,@aa:16 3 2 BNOT #xx:3,@aa:32 4 2 BNOT Rn,Rd 1 BNOT Rn,@ERd 2 2 BNOT Rn,@aa:8 2 2 BNOT Rn,@aa:16 3 2 BNOT Rn,@aa:32 4 2 BOR #xx:3,Rd 1 BOR #xx:3,@ERd 2 1 BOR #xx:3,@
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Appendix A Instruction Set Instruction BTST BXOR CLRMAC CMP Mnemonic Branch Byte Instruction Address Stack Data Fetch Read Operation Access Word Data Access Internal Operation I M N BTST #xx:3,Rd 1 BTST #xx:3,@ERd 2 1 2 1 3 1 BTST #xx:3,@aa:32 4 1 BTST Rn,Rd 1 BTST Rn,@ERd 2 1 BTST Rn,@aa:8 2 1 BTST Rn,@aa:16 3 1 BTST Rn,@aa:32 4 1 BXOR #xx:3,Rd 1 BXOR #xx:3,@ERd 2 1 BXOR #xx:3,@aa:8 2 1 BXOR #xx:
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Instruction EEPMOV EXTS EXTU INC JMP JSR LDC Mnemonic Branch Byte Instruction Address Stack Data Fetch Read Operation Access Word Data Access Internal Operation I M N EEPMOV.B 2 EEPMOV.W 2 EXTS.W Rd 1 EXTS.L ERd 1 EXTU.W Rd 1 EXTU.L ERd 1 INC.B Rd 1 INC.W #1/2,Rd 1 INC.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Appendix A Instruction Set Branch Byte Instruction Address Stack Data Fetch Read Operation Access Word Data Access Internal Operation M N Instruction Mnemonic I LDM*5 LDM.L @SP+, (ERn-ERn+1) 2 4 1 LDM.L @SP+, (ERn-ERn+2) 2 6 1 LDM.L @SP+, (ERn-ERn+3) 2 8 1 LDMAC ERs,MACH 1 LDMAC ERs,MACL 1 MAC @ERn+,@ERm+ 2 LDMAC MAC MOV J K L 1*3 1*3 2 MOV.B #xx:8,Rd 1 MOV.B Rs,Rd 1 MOV.B @ERs,Rd 1 1 MOV.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Appendix A Instruction Set Branch Byte Instruction Address Stack Data Fetch Read Operation Access Word Data Access Internal Operation M N Instruction Mnemonic I J K L MOV MOV.W Rs,@(d:16,ERd) 2 1 MOV.W Rs,@(d:32,ERd) 4 1 MOV.W Rs,@-ERd 1 1 MOV.W Rs,@aa:16 2 1 MOV.W Rs,@aa:32 3 1 MOV.L #xx:32,ERd 3 MOV.L ERs,ERd 1 MOV.L @ERs,ERd 2 2 MOV.L @(d:16,ERs),ERd 3 2 MOV.L @(d:32,ERs),ERd 5 2 MOV.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Appendix A Instruction Set Branch Byte Instruction Address Stack Data Fetch Read Operation Access Word Data Access Internal Operation M N Instruction Mnemonic I OR OR.B #xx:8,Rd 1 OR.B Rs,Rd 1 OR.W #xx:16,Rd 2 OR.W Rs,Rd 1 ORC POP PUSH ROTL ROTR ROTXL J K L OR.L #xx:32,ERd 3 OR.L ERs,ERd 2 ORC #xx:8,CCR 1 ORC #xx:8,EXR 2 POP.W Rn 1 1 1 POP.L ERn 2 2 1 PUSH.W Rn 1 1 1 PUSH.L ERn 2 2 1 ROTL.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Appendix A Instruction Set Branch Byte Instruction Address Stack Data Fetch Read Operation Access Word Data Access Internal Operation M N Instruction Mnemonic I ROTXR ROTXR.B Rd 1 ROTXR.B #2,Rd 1 ROTXR.W Rd 1 ROTXR.W #2,Rd 1 J K L ROTXR.L ERd 1 ROTXR.L #2,ERd 1 RTE RTE 2 2/3*1 1 RTS RTS 2 2 1 SHAL SHAL.B Rd 1 SHAL.B #2,Rd 1 SHAL.W Rd 1 SHAL.W #2,Rd 1 SHAL.L ERd 1 SHAL.L #2,ERd 1 SHAR.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Appendix A Instruction Set Branch Byte Instruction Address Stack Data Fetch Read Operation Access Word Data Access Internal Operation I M N Instruction Mnemonic STC STC.B CCR,Rd 1 STC.B EXR,Rd 1 STC.W CCR,@ERd 2 1 STC.W EXR,@ERd 2 1 STM*5 STMAC SUB L 1 STC.W EXR,@(d:16,ERd) 3 1 STC.W CCR,@(d:32,ERd) 5 1 STC.W EXR,@(d:32,ERd) 5 1 STC.W CCR,@-ERd 2 1 1 STC.W EXR,@-ERd 2 1 1 STC.W CCR,@aa:16 3 1 STC.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Appendix A Instruction Set Branch Byte Instruction Address Stack Data Fetch Read Operation Access Word Data Access Internal Operation M N Instruction Mnemonic I XOR XOR.B #xx:8,Rd 1 XOR.B Rs,Rd 1 XOR.W #xx:16,Rd 2 XOR.W Rs,Rd 1 XORC XOR.L #xx:32,ERd 3 XOR.L ERs,ERd 2 XORC #xx:8,CCR 1 XORC #xx:8,EXR 2 J K L Notes: 1. 2 when EXR is invalid, 3 when EXR is valid. 2. When n bytes of data are transferred. 3.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Appendix A Instruction Set A.5 Bus States during Instruction Execution Table A.6 indicates the types of cycles that occur during instruction execution by the CPU. See table A.4 for the number of states per cycle.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Appendix A Instruction Set Figure A.1 shows timing waveforms for the address bus and the RD, HWR, and LWR signals during execution of the above instruction with an 8-bit bus, using three-state access with no wait states.
Instruction ADD.B #xx:8,Rd ADD.B Rs,Rd ADD.W #xx:16,Rd ADD.W Rs,Rd ADD.L #xx:32,ERd ADD.L ERs,ERd ADDS #1/2/4,ERd ADDX #xx:8,Rd ADDX Rs,Rd AND.B #xx:8,Rd AND.B Rs,Rd AND.W #xx:16,Rd AND.W Rs,Rd AND.L #xx:32,ERd AND.
1 R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W 2nd Instruction BLE d:8 BRA d:16 (BT d:16) BRN d:16 (BF d:16) BHI d:16 BLS d:16 BCC d:16 (BHS d:16) BCS d:16 (BLO d:16) BNE d:16 BEQ d:16 BVC d:16 BVS d:16 BPL d:16 BMI d:16 BGE d:16 BLT d:16 BGT d:16 BLE d:16 BCLR #xx:3,Rd BCLR #xx:3,@ERd BCLR #xx:3,@aa:8 BCLR #xx:3,@aa:16 R01UH0166EJ0600 Rev. 6.
Instruction BCLR #xx:3,@aa:32 BCLR Rn,Rd BCLR Rn,@ERd BCLR Rn,@aa:8 BCLR Rn,@aa:16 BCLR Rn,@aa:32 BIAND #xx:3,Rd BIAND #xx:3,@ERd BIAND #xx:3,@aa:8 BIAND #xx:3,@aa:16 BIAND #xx:3,@aa:32 BILD #xx:3,Rd BILD #xx:3,@ERd BILD #xx:3,@aa:8 BILD #xx:3,@aa:16 BILD #xx:3,@aa:32 BIOR #xx:3,Rd BIOR #xx:3,@ERd BIOR #xx:3,@aa:8 BIOR #xx:3,@aa:16 BIOR #xx:3,@aa:32 BIST #xx:3,Rd BIST #xx:3,@ERd BIST #xx:3,@aa:8 BIST #xx:3,@aa:16 BIST #xx:3,@aa:32 BIXOR #xx:3,Rd BIXOR #xx:3,@ERd BIXOR #xx:3,@aa:8 BIXOR #xx:3,@aa:16 BIXOR #x
1 R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W 2nd Instruction BNOT #xx:3,@ERd BNOT #xx:3,@aa:8 BNOT #xx:3,@aa:16 BNOT #xx:3,@aa:32 BNOT Rn,Rd BNOT Rn,@ERd BNOT Rn,@aa:8 BNOT Rn,@aa:16 BNOT Rn,@aa:32 BOR #xx:3,Rd BOR #xx:3,@ERd BOR #xx:3,@aa:8 BOR #xx:3,@aa:16 BOR #xx:3,@aa:32 BSET #xx:3,
1 R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W NEXT R:W NEXT R:W 2nd R:W NEXT R:W 2nd R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W 2nd R:W 2nd R:W NEXT R:W NEXT R:W 2nd R:W 2nd R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT Instruction BTST #xx:3,@aa:8 BTST #xx:3,@aa:16 BTST #xx:3,@aa:32 BTST Rn,Rd BTST Rn,@ERd BTST Rn,@aa:8 BTST Rn,@aa:16 BTST Rn,@aa:32 BXOR #xx:3,Rd BXOR #xx:3,@ERd BXOR #xx:3,@aa:8 BXOR #xx:3,@aa:16 BXOR
R01UH0166EJ0600 Rev. 6.00 Mar 02, 2011 R:W NEXT R:W NEXT R:W 2nd R:W NEXT R:W NEXT R:W 2nd R:W NEXT R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd JMP @@aa:8 JSR @ERn JSR @aa:24 JSR @@aa:8 LDC #xx:8,CCR LDC #xx:8,EXR LDC Rs,CCR LDC Rs,EXR LDC @ERs,CCR LDC @ERs,EXR LDC @(d:16,ERs),CCR LDC @(d:16,ERs),EXR LDC @(d:32,ERs),CCR LDC @(d:32,ERs),EXR LDC @ERs+,CCR LDC @ERs+,EXR LDC @aa:16,CCR LDC @aa:16,EXR LDC @aa:32,CCR LDC @aa:32,EXR LDM.
1 R:W NEXT R:W 2nd R:W NEXT R:W NEXT R:W NEXT R:W 2nd R:W 2nd R:W NEXT R:W NEXT R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W NEXT R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W NEXT R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd Instruction LDMAC ERs,MACL MAC @ERn+,@ERm+ MOV.B #xx:8,Rd MOV.B Rs,Rd MOV.B @ERs,Rd MOV.B @(d:16,ERs),Rd MOV.B @(d:32,ERs),Rd MOV.B @ERs+,Rd Page 1210 of 1434 MOV.B @aa:8,Rd MOV.B @aa:16,Rd MOV.B @aa:32,Rd MOV.B Rs,@ERd MOV.
Mar 02, 2011 R01UH0166EJ0600 Rev. 6.00 MOV.L ERs,@aa:16 MOV.L ERs,@aa:32 MOVFPE @aa:16,Rd MOVTPE Rs,@aa:16 MULXS.B Rs,Rd MULXS.W Rs,ERd MULXU.B Rs,Rd MULXU.W Rs,ERd NEG.B Rd NEG.W Rd NEG.L ERd NOP NOT.B Rd NOT.W Rd NOT.L ERd OR.B #xx:8,Rd OR.B Rs,Rd OR.W #xx:16,Rd OR.W Rs,Rd OR.L #xx:32,ERd OR.L ERs,ERd ORC #xx:8,CCR ORC #xx:8,EXR MOV.L @aa:16,ERd MOV.L @aa:32,ERd MOV.L ERs,@ERd MOV.L ERs,@(d:16,ERd) MOV.L ERs,@(d:32,ERd) MOV.L ERs,@–ERd Instruction MOV.L #xx:32,ERd MOV.L ERs,ERd MOV.L @ERs,ERd MOV.
1 R:W NEXT R:W 2nd R:W NEXT R:W 2nd R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT Instruction POP.W Rn POP.L ERn PUSH.W Rn PUSH.L ERn ROTL.B Rd ROTL.B #2,Rd ROTL.W Rd ROTL.W #2,Rd ROTL.L ERd ROTL.L #2,ERd ROTR.B Rd ROTR.B #2,Rd ROTR.W Rd ROTR.W #2,Rd ROTR.L ERd ROTR.L #2,ERd ROTXL.B Rd ROTXL.B #2,Rd ROTXL.
R01UH0166EJ0600 Rev. 6.00 Mar 02, 2011 R:W 2nd R:W 2nd R:W 2nd STC EXR,@–ERd STC CCR,@aa:16 STC EXR,@aa:16 1 R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd Instruction SHAL.B #2,Rd SHAL.W Rd SHAL.W #2,Rd SHAL.L ERd SHAL.L #2,ERd SHAR.B Rd SHAR.B #2,Rd SHAR.
Page 1214 of 1434 R:W NEXT R:W NEXT R:W NEXT R:W 2nd R:W NEXT R:W 2nd R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W 2nd R:W NEXT R:W NEXT R:W NEXT R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W NEXT R:W 2nd STMAC MACH,ERd STMAC MACL,ERd SUB.B Rs,Rd SUB.W #xx:16,Rd SUB.W Rs,Rd SUB.L #xx:32,ERd SUB.L ERs,ERd SUBS #1/2/4,ERd SUBX #xx:8,Rd SUBX Rs,Rd TAS @ERd*8 TRAPA #x:2 XOR.B #xx8,Rd XOR.B Rs,Rd XOR.W #xx:16,Rd XOR.W Rs,Rd XOR.L #xx:32,ERd XOR.L ERs,ERd XORC #xx:8,CCR XORC #xx:8,EXR STM.L(ERn–ERn+3),@–SP*9 R:W 2nd STM.
1 R:W VEC Mar 02, 2011 3 4 Internal operation, R:W*5 1 state Internal operation, W:W stack (L) W:W stack (H) 1 state 2 R:W VEC+2 W:W stack (EXR) 5 R:W:M VEC 6 R:W VEC+2 7 9 Internal operation, R:W*7 1 state 8 Notes: 1. EAs is the contents of ER5. EAd is the contents of ER6. 2. EAs is the contents of ER5. EAd is the contents of ER6. Both registers are incremented by 1 after execution of the instruction. n is the initial value of R4L or R4. If n = 0, these bus cycles are not executed. 3.
Appendix A Instruction Set A.6 H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Condition Code Modification This section indicates the effect of each CPU instruction on the condition code. The notation used in the table is defined below.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Table A.7 Instruction Appendix A Instruction Set Condition Code Modification H N Z V C Definition H = Sm–4 · Dm–4 + Dm–4 · Rm–4 + Sm–4 · Rm–4 ADD N = Rm Z = Rm · Rm–1 · ...... · R0 V = Sm · Dm · Rm + Sm · Dm · Rm C = Sm · Dm + Dm · Rm + Sm · Rm ADDS — — — — — H = Sm–4 · Dm–4 + Dm–4 · Rm–4 + Sm–4 · Rm–4 ADDX N = Rm Z = Z' · Rm · ......
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Appendix A Instruction Set Instruction H N Z V C CLRMAC — — — — — Definition H = Sm–4 · Dm–4 + Dm–4 · Rm–4 + Sm–4 · Rm–4 CMP N = Rm Z = Rm · Rm–1 · ...... · R0 V = Sm · Dm · Rm + Sm · Dm · Rm C = Sm · Dm + Dm · Rm + Sm · Rm DAA * N = Rm * Z = Rm · Rm–1 · ...... · R0 C: decimal arithmetic carry DAS * N = Rm * Z = Rm · Rm–1 · ...... · R0 C: decimal arithmetic borrow DEC — — N = Rm Z = Rm · Rm–1 · ......
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 N Z V Appendix A Instruction Set Instruction H MAC — — — — — MOV — 0 C — Definition N = Rm Z = Rm · Rm–1 · ...... · R0 MOVFPE Can not be used in H8S/2633 Group MOVTPE MULXS — — — N = R2m Z = R2m · R2m–1 · ...... · R0 MULXU — — — — — NEG H = Dm–4 + Rm–4 N = Rm Z = Rm · Rm–1 · ...... · R0 V = Dm · Rm C = Dm + Rm NOP — — — — — NOT — 0 — N = Rm Z = Rm · Rm–1 · ...... · R0 OR — 0 — N = Rm Z = Rm · Rm–1 · ...
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Appendix A Instruction Set Instruction H ROTXL — N Z V C 0 Definition N = Rm Z = Rm · Rm–1 · ...... · R0 C = Dm (1-bit shift) or C = Dm–1 (2-bit shift) ROTXR — 0 N = Rm Z = Rm · Rm–1 · ...... · R0 C = D0 (1-bit shift) or C = D1 (2-bit shift) RTE Stores the corresponding bits of the result. RTS — — — — — SHAL — N = Rm Z = Rm · Rm–1 · ......
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Instruction H N Z V Appendix A Instruction Set C Definition H = Sm–4 · Dm–4 + Dm–4 · Rm–4 + Sm–4 · Rm–4 SUB N = Rm Z = Rm · Rm–1 · ...... · R0 V = Sm · Dm · Rm + Sm · Dm · Rm C = Sm · Dm + Dm · Rm + Sm · Rm SUBS — — — — — H = Sm–4 · Dm–4 + Dm–4 · Rm–4 + Sm–4 · Rm–4 SUBX N = Rm Z = Z' · Rm · ...... · R0 V = Sm · Dm · Rm + Sm · Dm · Rm C = Sm · Dm + Dm · Rm + Sm · Rm 1 TAS* — 0 — N = Dm Z = Dm · Dm–1 · ......
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Appendix B Internal I/O Register Appendix B Internal I/O Register B.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Register Address Name H'FDD4 Bit 7 Bit 6 Appendix B Internal I/O Register Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SSR3 TDRE RDRF ORER FER PER TEND MPB MPBT SSR3 TDRE RDRF ORER ERS PER TEND MPB MPBT H'FDD5 RDR3 H'FDD6 SCMR3 — — — — SDIR SINV — SMIF H'FDD8 SMR4 C/A CHR PE O/E STOP MP CKS1 CKS0 SMR4 GM BLK PE O/E BCP1 BCP0 CKS1 CKS0 TIE RIE TE RE MPIE TEIE CKE1 CKE0 H'FDD9 H'FDDA
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Appendix B Internal I/O Register Register Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name H'FE16 DTCERA DTCEA7 DTCEA6 DTCEA5 DTCEA4 DTCEA3 DTCEA2 DTCEA1 DTCEA0 DTC H'FE17 DTCERB DTCEB7 DTCEB6 DTCEB5 DTCEB4 DTCEB3 DTCEB2 DTCEB1 DTCEB0 H'FE18 DTCERC DTCEC7 DTCEC6 DTCEC5 DTCEC4 DTCEC3 DTCEC2 DTCEC1 DTCEC0 H'FE19 DTCERD DTCED7 DTCED6 DTCED5 DTCED4 DTCED3 DTCED2 DTCED1 DTCED0 H'FE1A DTCERE DTCEE7
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Register Address Name Bit 7 Bit 6 Appendix B Internal I/O Register Bit 5 Bit 4 Bit 3 Bit 2 Data Bus Width (bits) Bit 1 Bit 0 Module Name TPU3 16 TPU4 16 TPU5 16 H'FE80 TCR3 CCLR2 CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 H'FE81 TMDR3 — — BFB BFA MD3 MD2 MD1 MD0 H'FE82 TIOR3H IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0 H'FE83 TIOR3L IOD3 IOD2 IOD1 IOD0 IOC3 IOC2 IOC1 IOC0 H'FE84 TIER3
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Appendix B Internal I/O Register Register Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name Data Bus Width (bits) TPU 16 Interrupt controller 8 Bus controller 8 H'FEB0 TSTR — — CST5 CST4 CST3 CST2 CST1 CST0 H'FEB1 TSYR — — SYNC5 SYNC4 SYNC3 SYNC2 SYNC1 SYNC0 H'FEC0 IPRA — IPR6 IPR5 IPR4 — IPR2 IPR1 IPR0 H'FEC1 IPRB — IPR6 IPR5 IPR4 — IPR2 IPR1 IPR0 H'FEC2 IPRC
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Register Address Name H'FEEC Bit 7 Bit 6 Appendix B Internal I/O Register Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 IOAR0B Module Name Data Bus Width (bits) DMAC 16 Port 8 TPU0 16 H'FEED H'FEEE ETCR0B H'FEEF H'FEF0 MAR1AH — — — — — — — — — — — — — — — — H'FEF1 H'FEF2 MAR1AL H'FEF3 H'FEF4 IOAR1A H'FEF5 H'FEF6 ETCR1A H'FEF7 H'FEF8 MAR1BH H'FEF9 H'FEFA MAR1BL H'FEFB H'FEFC IOAR1B H'FEFD H'FEFE ET
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Appendix B Internal I/O Register Bit 0 Module Name Data Bus Width (bits) IOA1 IOA0 TPU0 16 IOC1 IOC0 TPU1 16 TPU2 16 Register Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 H'FF12 TIOR0H IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 H'FF13 TIOR0L IOD3 IOD2 IOD1 IOD0 IOC3 IOC2 H'FF14 TIER0 TTGE — — TCIEV TGIED TGIEC TGIEB TGIEA H'FF15 TSR0 — — — TCFV TGFD TGFC TGFB TGFA H'FF16 TCNT0 — CCLR1
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Appendix B Internal I/O Register Register Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name Data Bus Width (bits) DMAC 8 H'FF60 DMAWER — — — — WE1B WE1A WE0B WE0A H'FF61 DMATCR — — TEE1 TEE0 — — — — H'FF62 DMACR0A DTSZ DTID RPE DTDIR DTF3 DTF2 DTF1 DTF0 H'FF63 DMACR0B DTSZ DTID RPE DTDIR DTF3 DTF2 DTF1 DTF0 H'FF64 DMACR1A DTSZ DTID RPE DTDIR DTF3 DTF2 DTF
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Appendix B Internal I/O Register Register Address Name H'FF7E Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SCMR0 — — — — SDIR SINV — SMIF ICDR0/ SARX0 ICDR7/ SVAX6 ICDR6/ SVAX5 ICDR5/ SVAX4 ICDR4/ SVAX3 ICDR3/ SVAX2 ICDR2/ SVAX1 ICDR1/ SVAX0 ICDR0/ FSX H'FF7F ICMR0/ SAR0 MLS/ SVA6 WAIT/ SVA5 CKS2/ SVA4 CKS1/ SVA3 CKS0/ SVA2 BC2/ SVA1 BC1/ SVA0 BC0/FS H'FF80 SMR1 C/A CHR PE O/E STOP MP CKS1 CK
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Register Address Name H'FFA2 (write) TCSR1/ TCNT1 H'FFA3 (read) TCNT1 H'FFA4 DADR0 Appendix B Internal I/O Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name OVF WT/IT TME PSS RST/ NMI CKS2 CKS1 CKS0 WDT1 Data Bus Width (bits) 16 D/A0, D/A1 8 H'FFA5 DADR1 H'FFA6 DACR01 DAOE1 DAOE0 DAE — — — — H'FFA8 FLMCR1 FWE SWE1 ESU1 PSU1 EV1 PV1 E1 P1 H'FFA9 FLMCR2 FLER — — — — —
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Appendix B Internal I/O Register B.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Register Address Name Bit 7 Bit 6 Appendix B Internal I/O Register Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name H'FE30 P1DDR P17DDR P16DDR P15DDR P14DDR P13DDR P12DDR P11DDR P10DDR Port H'FE32 P3DDR P37DDR P36DDR P35DDR P34DDR P33DDR P32DDR P31DDR P30DDR H'FE36 P7DDR P77DDR P76DDR P75DDR P74DDR P73DDR P72DDR P71DDR P70DDR H'FE39 PADDR — H'FE3A PBDDR PB7DDR PB6DDR PB5DDR PB4DDR PB3DDR PB2DDR PB1DDR PB0DDR H'FE3
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Appendix B Internal I/O Register Register Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Data Bus Width (bits) Bit 1 Bit 0 Module Name TPU4 16 TPU5 16 TPU 16 Interrupt controller 8 H'FE90 TCR4 — CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 H'FE91 TMDR4 — — — — MD3 MD2 MD1 MD0 H'FE92 TIOR4 IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0 H'FE94 TIER4 TTGE — TCIEU TCIEV — — TGIEB TGIEA H'FE95 T
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Appendix B Internal I/O Register Register Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 H'FED0 ABWCR ABW7 ABW6 ABW5 ABW4 ABW3 ABW2 ABW1 ABW0 H'FED1 ASTCR AST7 AST6 AST5 AST4 AST3 AST2 AST1 AST0 H'FED2 WCRH W71 W70 W61 W60 W51 W50 W41 W40 H'FED3 WCRL W31 W30 W21 W20 W11 W10 W01 W00 BRSTRM BRSTS1 BRSTS0 RMTS2 H'FED4 BCRH ICIS1 ICIS0 RMTS1 RMST0 H'FED5 BCRL BRLE BREQO
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Appendix B Internal I/O Register Register Address Name H'FF1A Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TGR0B Module Name Data Bus Width (bits) TPU0 16 TPU1 16 TPU2 16 WDT0 16 H'FF1B H'FF1C TGR0C H'FF1D H'FF1E TGR0D H'FF1F H'FF20 TCR1 — CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 H'FF21 TMDR1 — — — — MD3 MD2 MD1 MD0 H'FF22 TIOR1 IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0 H'FF24 TIER1
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Appendix B Internal I/O Register Register Address Name Bit 7 Bit 6 Bit 5 Bit 4 H'FF78 H'FF79 Bit 3 Bit 2 Bit 1 Bit 0 SMR0 C/A CHR PE O/E STOP MP CKS1 CKS0 SMR0 GM BLK PE O/E BCP1 BCP0 CKS1 CKS0 ICCR0 ICE IEIC MST TRS ACKE BBSY IRIC SCP ICSR0 ESTP STOP IRTR AASX AL AAS ADZ ACKB SCR0 TIE RIE TE RE MPIE TEIE CKE1 CKE0 H'FF7B TDR0 H'FF7C SSR0 TDRE RDRF ORER FER PER TEND MPB M
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Appendix B Internal I/O Register Register Address Name Bit 7 Bit 6 Bit 5 Bit 4 H'FF88 SMR2 C/A CHR PE SMR2 GM BLK PE TIE RIE TE H'FF89 Bit 2 Bit 1 Bit 0 O/E STOP MP CKS1 CKS0 O/E BCP1 BCP0 CKS1 CKS0 RE MPIE TEIE CKE1 CKE0 Data Bus Width (bits) 8 SCI2, Smart card interface BRR2 H'FF8A SCR2 H'FF8B TDR2 H'FF8C Bit 3 Module Name SSR2 TDRE RDRF ORER FER PER TEND MPB MPBT SSR2 TDRE RDRF OR
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 B.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Appendix B Internal I/O Register IrCR—IrDA Control Register Bit : : SCI0, IrDA 7 6 5 4 3 2 1 0 IrE IrCKS2 IrCKS1 IrCKS0 — — — — 0 0 0 0 0 0 0 0 R/W R/W R/W R/W — — — — Initial value : R/W H'FDB0 IrDA clock select 2 to 0 Bit 6 IrCKS2 0 Bit 5 IrCKS1 0 1 1 0 1 Bit 4 IrCKS0 0 1 0 1 0 1 0 1 Description B × 3/16 (3/16ths of bit rate) φ/2 φ/4 φ/8 φ/16 φ/32 φ/64 φ/128 IrDA enable 0 1 TxD0/IrTxD and RxD0/
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Appendix B Internal I/O Register DDCSWR—DDC Switch Register Bit : Initial value : R/W : H'FDB5 IIC 7 6 5 4 3 2 1 0 — — — — CLR3 CLR2 CLR1 CLR0 0 0 0 0 1 1 1 1 W*2 W*2 W*2 W*2 R/(W)*1 R/(W)*1 R/(W)*1 R/(W)*1 Reserved bit IIC clear 3 to 0 CLR3 CLR2 CLR1 CLR0 0 0 — — Setting prohibited 1 0 0 Setting prohibited 1 IIC0 internal latch cleared 1 0 IIC1 internal latch cleared IIC0 and IIC1 internal latch clear
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Appendix B Internal I/O Register DACR0—PWM (D/A) Control Register 0 DACR1—PWM (D/A) Control Register 1 Bit : : PWM0 PWM1 7 6 5 4 3 2 1 0 TEST PWME — — OEB OEA OS CKS Initial value : R/W H'FDB8 H'FDBC 0 0 1 1 0 0 0 0 R/W R/W — — R/W R/W R/W R/W Clock select 0 1 Resolution (T) = system clock cycle (tcyc). Resolution (T) = system clock cycle (tcyc) × 2. Output select 0 1 Direct PWM output.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Appendix B Internal I/O Register PWM0 PWM0 PWM0 PWM0 PWM1 PWM1 PWM1 PWM1 H'FDB8 H'FDB9 H'FDBA H'FDBB H'FDBC H'FDBD H'FDBE H'FDBF DADRAH0—PWM (D/A) Data Register AH0 DADRAL0—PWM (D/A) Data Register AL0 DADRBH0—PWM (D/A) Data Register BH0 DADRBL0—PWM (D/A) Data Register BL0 DADRAH1—PWM (D/A) Data Register AH1 DADRAL1—PWM (D/A) Data Register AL1 DADRBH1—PWM (D/A) Data Register BH1 DADRBL1—PWM (D/A) Data Register BL1 DADRH DADRL Bit (CPU
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Appendix B Internal I/O Register PWM0 PWM0 PWM1 PWM1 H'FDBA H'FDBB H'FDBE H'FDBF DACNTH0—PWM (D/A) Counter H0 DACNTL0—PWM (D/A) Counter L0 DACNTH1—PWM (D/A) Counter H1 DACNTL1—PWM (D/A) Counter L1 DACNTH Bit (CPU) DACNTL : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit (counter) : 7 6 5 4 3 2 1 0 8 9 10 11 12 13 — — REGS Initial value : R/W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 : R/W R/W R/W R/W R
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Appendix B Internal I/O Register Bit : 7 6 5 4 3 2 1 0 CMIEB CMIEA OVIE CCLR1 CCLR0 CKS2 CKS1 CKS0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Initial value : R/W TMR2 TMR3 TMR0 TMR1 H'FDC0 H'FDC1 H'FF68 H'FF69 TCR2—Timer Control Register 2 TCR3—Timer Control Register 3 TCR0—Timer Control Register 0 TCR1—Timer Control Register 1 : Timer overflow interrupt enable 0 OVF interrupt request (OVI) di
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Appendix B Internal I/O Register TCSR0 Bit : Initial value : R/W : 7 6 5 4 3 2 1 0 CMFB CMFA OVF ADTE OS3 OS2 OS1 OS0 0 R/(W)* 0 R/(W)* 0 R/(W)* 0 0 0 0 0 R/W R/W R/W R/W R/W TCSR1, TCSR3 Bit : Initial value : R/W : TCSR2 Bit : Initial value : R/W : TMR2 TMR3 TMR0 TMR1 H'FDC2 H'FDC3 H'FF6A H'FF6B TCSR2—Timer Control/Status Register 2 TCSR3—Timer Control/Status Register 3 TCSR0—Timer Control/Status Re
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Appendix B Internal I/O Register TCORA0 (TCORA2) Bit TMR2 TMR3 TMR0 TMR1 H'FDC4 H'FDC5 H'FF6C H'FF6D TCORA2—Time Constant Register A2 TCORA3—Time Constant Register A3 TCORA0—Time Constant Register A0 TCORA1—Time Constant Register A1 TCORA1 (TCORA3) : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value : 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R/W : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Appendix B Internal I/O Register Bit : Initial value : R/W : SCI3 SCI4 SCI0 SCI1 SCI2 H'FDD0 H'FDD8 H'FF78 H'FF80 H'FF88 SMR3—Serial Mode Register 3 SMR4—Serial Mode Register 4 SMR0—Serial Mode Register 0 SMR1—Serial Mode Register 1 SMR2—Serial Mode Register 2 7 6 5 4 3 2 1 0 C/A CHR PE O/E STOP MP CKS1 CKS0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Clock select 1 and 0 CKS1 0 1 CKS0 0 1 0 1 Des
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Appendix B Internal I/O Register Bit : Initial value : R/W : Smart Card Interface H'FDD0 H'FDD8 H'FF78 H'FF80 H'FF88 SMR3—Serial Mode Register 3 SMR4—Serial Mode Register 4 SMR0—Serial Mode Register 0 SMR1—Serial Mode Register 1 SMR2—Serial Mode Register 2 7 6 5 4 3 2 1 0 GM BLK PE O/E BCP1 BCP0 CKS1 CKS0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Basic clock pulse 1, 0 BCP1 BCP0 0 0 32 clock 1
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Appendix B Internal I/O Register Bit SCI3 SCI4 SCI0 SCI1 SCI2 H'FDD1 H'FDD9 H'FF79 H'FF81 H'FF89 BRR3—Bit Rate Register 3 BRR4—Bit Rate Register 4 BRR0—Bit Rate Register 0 BRR1—Bit Rate Register 1 BRR2—Bit Rate Register 2 : 7 6 5 4 3 2 1 0 Initial value : 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W : Page 1250 of 1434 R01UH0166EJ0600 Rev. 6.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Appendix B Internal I/O Register Bit : Initial value : R/W : SCI3 SCI4 SCI0 SCI1 SCI2 H'FDD2 H'FDDA H'FF7A H'FF82 H'FF8A SCR3—Serial Control Register 3 SCR4—Serial Control Register 4 SCR0—Serial Control Register 0 SCR1—Serial Control Register 1 SCR2—Serial Control Register 2 7 6 5 4 3 2 1 0 TIE RIE TE RE MPIE TEIE CKE1 CKE0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Clock enable 1, 0 Bit 1 CKE1
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Appendix B Internal I/O Register Bit SCI3 SCI4 SCI0 SCI1 SCI2 H'FDD3 H'FDDB H'FF7B H'FF83 H'FF8B TDR3—Transmit Data Register 3 TDR4—Transmit Data Register 4 TDR0—Transmit Data Register 0 TDR1—Transmit Data Register 1 TDR2—Transmit Data Register 2 : 7 6 5 4 3 2 1 0 Initial value : 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W : Page 1252 of 1434 R01UH0166EJ0600 Rev. 6.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Appendix B Internal I/O Register Bit : Initial value : R/W : SCI3 SCI4 SCI0 SCI1 SCI2 H'FDD4 H'FDDC H'FF7C H'FF84 H'FF8C SSR3—Serial Status Register 3 SSR4—Serial Status Register 4 SSR0—Serial Status Register 0 SSR1—Serial Status Register 1 SSR2—Serial Status Register 2 7 6 5 4 3 2 1 0 TDRE RDRF ORER FER PER TEND MPB MPBT 1 0 0 0 0 R/(W)*1 R/(W)*1 R/(W)*1 R/(W)*1 R/(W)*1 1 0 0 R R R/W Multiprocessor bit t
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Appendix B Internal I/O Register Bit : 7 SCI3 SCI4 SCI0 SCI1 SCI2 H'FDD5 H'FDDD H'FF7D H'FF85 H'FF8D RDR3—Receive Data Register 3 RDR4—Receive Data Register 4 RDR0—Receive Data Register 0 RDR1—Receive Data Register 1 RDR2—Receive Data Register 2 6 5 4 3 2 1 0 Initial value : 0 0 0 0 0 0 0 0 R/W R R R R R R R R : Bit : SCI3 SCI4 SCI0 SCI1 SCI2 H'FDD6 H'FDDE H'FF7E H'FF86 H'FF8E SCMR3—Smart Card Mode Registe
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Appendix B Internal I/O Register SBYCR—Standby Control Register Bit : Initial value : R/W : H'FDE4 System 7 6 5 4 3 2 1 0 SSBY STS2 STS1 STS0 OPE — — — 0 0 0 0 1 0 0 0 R/W R/W R/W R/W R/W — — — Output port enable 0 In software standby mode, watch mode, and during direct transfer, the address bus and bus control signal are in the high-impedance state.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Appendix B Internal I/O Register SYSCR—System Control Register Bit : Initial value : R/W : H'FDE5 7 6 5 4 MACS — INTM1 INTM0 0 0 0 0 0 R/W — R/W R/W R/W 3 System 1 0 — RAME 0 0 1 R/W — R/W 2 NMIEG MRESE NMI edge select 0 Interrupt request issued on falling edge of NMI input. 1 Interrupt request issued on rising edge of NMI input.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Appendix B Internal I/O Register SCKCR—System Clock Control Register Bit : System 7 6 5 4 3 2 1 0 PSTOP — — — STCS SCK2 SCK1 SCK0 0 0 0 0 0 0 0 0 R/W — — — R/W R/W R/W R/W : Initial value : R/W H'FDE6 System clock select 2 to 0 SCK2 0 SCK1 0 1 1 0 1 SCK0 0 1 0 1 0 1 — Bus master set to high-speed mode.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Appendix B Internal I/O Register MDCR—Mode Control Register Bit : Initial value : R/W : H'FDE7 System 7 6 5 4 3 2 1 0 — — — — — MDS2 MDS1 MDS0 1 0 0 0 0 —* —* —* R/W — — — — R R R Mode select 2 to 0 * Input level determined by mode pins. Note: * Determined by pins MD2 to MD0.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Appendix B Internal I/O Register MSTPCRC—Module Stop Control Register C Bit : 7 6 5 H'FDEA 4 3 System 2 1 0 MSTPC7 MSTPC6 MSTPC5 MSTPC4 MSTPC3 MSTPC2 MSTPC1 MSTPC0 Initial value : R/W : 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W Module stop R01UH0166EJ0600 Rev. 6.00 Mar 02, 2011 0 Module stop mode canceled. 1 Module stop mode enabled.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Appendix B Internal I/O Register PFCR—Pin Function Control Register Bit : System 7 6 5 4 3 2 1 0 CSS07 CSS36 BUZZE LCASS AE3 AE2 AE1 AE0 Initial value : R/W H'FDEB : 0 0 0 0 1/0 1/0 0 1/0 R/W R/W R/W R/W R/W R/W R/W R/W LCAS output pin select bit 0 LCAS signal output from PF2. 1 LCAS signal output from PF6. BUZZ output enable* 0 Functions as PF1 input pin. 1 Functions as BUZZ output pin.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Appendix B Internal I/O Register LPWRCR—Low-Power Control Register Bit : 7 6 H'FDEC 5 4 3 DTON*1 LSON*1 NESEL*1 SUBSTP*1 RFCUT*1 Initial value : R/W : System 2 1 0 — STC1 STC0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Frequency multiplier STC1 0 1 STC0 0 1 0 1 Description × 1 (initial value) ×2 ×4 Do not set.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Appendix B Internal I/O Register BARA—Break Address Register A BARB—Break Address Register B Bit : Initial value : R/W 31 ··· 24 — ··· — 23 — ··· 21 20 19 18 17 16 ··· 7 PBC PBC 6 5 4 3 2 1 0 BAA BAA BAA BAA BAA BAA BAA BAA BAA BAA BAA BAA BAA BAA BAA BAA ··· 7 6 5 4 3 2 1 0 23 22 21 20 19 18 17 16 Unde- ··· Unde- 0 fined fined : 22 H'FE00 H'FE04 0 0 0 0 0 0 0 — R/W R/W R/W R/W R/W R/W R/W R/W ··· 0
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Appendix B Internal I/O Register BCRA—Break Control Register A BCRB—Break Control Register B Bit : 7 6 CMFA CDA Initial value : R/W : H'FE08 H'FE09 5 4 PBC PBC 3 2 1 0 BAMRA2 BAMRA1 BAMRA0 CSELA1 CSELA0 BIEA 0 0 0 0 0 0 0 0 R/(W)* R/W R/W R/W R/W R/W R/W R/W CPU cycle/DTC cycle select A 0 When the CPU is the bus master, PC break performed. 1 When the CPU or DTC is the bus master, PC break performed.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Appendix B Internal I/O Register ISCRH—IRQ Sense Control Register H ISCRL—IRQ Sense Control Register L H'FE12 H'FE13 Interrupt Controller Interrupt Controller ISCRH Bit : 15 14 13 12 11 10 9 8 IRQ7SCB IRQ7SCA IRQ6SCB IRQ6SCA IRQ5SCB IRQ5SCA IRQ4SCB IRQ4SCA Initial value : R/W 0 0 0 0 0 0 0 0 : R/W R/W R/W R/W R/W R/W R/W R/W : 7 6 5 4 3 2 1 0 ISCRL Bit IRQ3SCB IRQ3SCA IRQ2SCB IRQ2SCA IRQ1SCB IRQ1SCA
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Appendix B Internal I/O Register ISR—IRQ Status Register Bit : : Interrupt Controller 7 6 5 4 3 2 1 0 IRQ7F IRQ6F IRQ5F IRQ4F IRQ3F IRQ2F IRQ1F IRQ0F 0 0 0 0 0 0 0 0 R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* Initial value : R/W H'FE15 IRQ7 to IRQ0 flag 0 [Clearing] (1) Writing 0 to flag IRQnF after reading IRQnF=1; (2) When interrupt exception processing is executed when set for LOW-le
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Appendix B Internal I/O Register DTCER—DTC Enable Register Bit : Initial value : R/W : H'FE16 to H'FE1E DTC 7 6 5 4 3 2 1 0 DTCE7 DTCE6 DTCE5 DTCE4 DTCE3 DTCE2 DTCE1 DTCE0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W DTC start enable DTCEn 0 DTC startup by interrupt disabled [Clearing conditions] • When data transmission ends with the DISEL bit =1.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Appendix B Internal I/O Register DTVECR—DTC Vector Register Bit : 7 6 H'FE1F 5 4 3 DTC 2 1 0 SWDTE DTVEC6 DTVEC5 DTVEC4 DTVEC3 DTVEC2 DTVEC1 DTVEC0 Initial value : R/W : 0 0 0 0 0 0 0 0 R/(W)*1 R/(W)*2 R/(W)*2 R/(W)*2 R/(W)*2 R/(W)*2 R/(W)*2 R/(W)*2 DTC software startup enable 0 DTC software startup disabled [Clearing conditions] • When DISEL=0 and the specified number of transmissions has not completed.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Appendix B Internal I/O Register PCR—PPG Output Control Register Bit : 7 H'FE26 6 5 4 PPG 3 2 1 0 G3CMS1 G3CMS0 G2CMS1 G2CMS0 G1CMS1 G1CMS0 G0CMS1 G0CMS0 Initial value : R/W : 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W Group 2 compare match select 1, 0 G2CMS1 G2CMS0 0 1 Pulse output group 2 output trigger 0 TPU channel 0 compare match 1 TPU channel 1 compare match 0 TPU channel 2 compare match 1 T
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Appendix B Internal I/O Register PMR—PPG Output Mode Register Bit : : PPG 7 6 5 4 G3INV G2INV G1INV G0INV 1 1 1 1 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Initial value : R/W H'FE27 3 2 G3NOV G2NOV 0 1 G1NOV G0NOV Group 0 inversion 0 Pulse output group 0 set for inverted output (pin output level is set LOW when PODRL=1).
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Appendix B Internal I/O Register NDERH—Next Data Enable Register H NDERL—Next Data Enable Register L H'FE28 H'FE29 PPG PPG NDERH Bit : 7 6 5 4 3 2 1 NDER15 NDER14 NDER13 NDER12 NDER11 NDER10 NDER9 Initial value : R/W : 0 NDER8 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Next data enable 15 to 8 NDER15 to NDER8 0 Pulse output PO15 to PO8 disabled (transfer from NDR15-NDR8 to POD15-POD8 disabled).
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Appendix B Internal I/O Register PODRH—Output Data Register H PODRL—Output Data Register L H'FE2A H'FE2B PPG PPG PODRH Bit : Initial value : R/W 7 6 5 4 3 2 1 0 POD15 POD14 POD13 POD12 POD11 POD10 POD9 POD8 0 0 0 0 0 0 0 0 : R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* : 7 6 5 4 3 2 1 0 POD7 POD6 POD5 POD4 POD3 POD2 POD1 POD0 0 0 0 0 0 0 0 0 R/(W)* R/(W)* R/(W)*
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Appendix B Internal I/O Register NDRH—Next Data Register H H'FE2C, H'FE2E PPG Same trigger for pulse output groups.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Appendix B Internal I/O Register NDRL—Next Data Register L H'FE2D, H'FE2F PPG Same trigger for pulse output groups.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Appendix B Internal I/O Register P3DDR—Port 3 Data Direction Register Bit : 7 6 5 H'FE32 4 3 Port 2 1 0 P37DDR P36DDR P35DDR P34DDR P33DDR P32DDR P31DDR P30DDR Initial value : 0 0 0 0 0 0 0 0 R/W W W W W W W W W : P7DDR—Port 7 Data Direction Register Bit : 7 6 5 H'FE36 4 3 Port 2 1 0 P77DDR P76DDR P75DDR P74DDR P73DDR P72DDR P71DDR P70DDR Initial value : 0 0 0 0 0 0 0 0 R/W W W W W W W
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Appendix B Internal I/O Register PDDDR—Port D Data Direction Register Bit : 7 6 5 H'FE3C 4 3 Port 2 1 0 PD7DDR PD6DDR PD5DDR PD4DDR PD3DDR PD2DDR PD1DDR PD0DDR Initial value : 0 0 0 0 0 0 0 0 R/W W W W W W W W W : PEDDR—Port E Data Direction Register Bit : 7 6 5 H'FE3D 4 3 Port 2 1 0 PE7DDR PE6DDR PE5DDR PE4DDR PE3DDR PE2DDR PE1DDR PE0DDR Initial value : 0 0 0 0 0 0 0 0 R/W W W W W W
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Appendix B Internal I/O Register PGDDR—Port G Data Direction Register Bit : 7 6 5 — — — H'FE3F 4 3 Port 2 1 0 PG4DDR PG3DDR PG2DDR PG1DDR PG0DDR Modes 4 and 5 Initial value : Undefined Undefined Undefined 1 0 0 0 0 R/W W W W W W : — — — Modes 6 and 7 Initial value : Undefined Undefined Undefined 0 0 0 0 0 R/W W W W W W : — — — PAPCR—Port A Pull-Up MOS Control Register Bit : 7 6 5 4 — — —
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Appendix B Internal I/O Register PDPCR—Port D Pull-Up MOS Control Register Bit : 7 6 5 4 H'FE43 3 Port 2 1 0 PD7PCR PD6PCR PD5PCR PD4PCR PD3PCR PD2PCR PD1PCR PD0PCR Initial value : R/W : 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W PEPCR—Port E Pull-Up MOS Control Register Bit : 7 6 5 4 H'FE44 3 Port 2 1 0 PE7PCR PE6PCR PE5PCR PE4PCR PE3PCR PE2PCR PE1PCR PE0PCR Initial value : R/W : 0 0 0 0
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Appendix B Internal I/O Register PBODR—Port B Open Drain Control Register Bit : 7 6 5 H'FE48 4 3 Port 2 1 0 PB7ODR PB6ODR PB5ODR PB4ODR PB3ODR PB2ODR PB1ODR PB0ODR Initial value : R/W : 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W PCODR—Port C Open Drain Control Register Bit : 7 6 5 H'FE49 4 3 Port 2 1 0 PC7ODR PC6ODR PC5ODR PC4ODR PC3ODR PC2ODR PC1ODR PC0ODR Initial value : R/W : Page 1278 of 1434
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Appendix B Internal I/O Register TCR0—Timer Control Register 0 TCR3—Timer Control Register 3 H'FF10 H'FE80 TPU0 TPU3 Channel 0: TCR0 Channel 3: TCR3 Bit : 7 6 5 CCLR2 CCLR1 CCLR0 Initial value : R/W : 4 3 CKEG1 CKEG0 2 1 0 TPSC2 TPSC1 TPSC0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Time prescaler 2, 1, 0 TCR0 TPSC2 TPSC1 TPSC0 0 1 0 0 Internal clock: counts on ø/1 1 Internal clock: counts
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Appendix B Internal I/O Register TMDR0—Timer Mode Register 0 TMDR3—Timer Mode Register 3 H'FF11 H'FE81 TPU0 TPU3 Channel 0: TMDR0 Channel 3: TMDR3 Bit : 7 6 5 4 3 2 1 0 — — BFB BFA MD3 MD2 MD1 MD0 Initial value : 1 1 0 0 0 0 0 0 R/W — — R/W R/W R/W R/W R/W R/W : Buffer operation B 0 Normal TGRB operation. 1 Buffer operation of TGRB and TGRD. Buffer operation A 0 Normal TGRA operation.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Appendix B Internal I/O Register TIOR3H—Timer I/O Control Register 3H Bit : Initial value : R/W : H'FE82 TPU3 7 6 5 4 3 2 1 0 IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W TGR3A I/O Control 0 0 0 1 1 0 1 0 TGR3A is Output disabled 1 output Initial output is 0 compare output 0 register 1 0 Output disabled 1 Initial output is 1 output 0 1 1 0 0 1 1
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Appendix B Internal I/O Register TIOR4—Timer I/O Control Register 4 Bit : Initial value : R/W : H'FE92 TPU4 7 6 5 4 3 2 1 0 IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W TGR4A I/O Control 0 0 0 1 1 0 1 0 TGR4A is Output disabled 1 output Initial output is 0 compare output 0 register 1 0 Output disabled 1 Initial output is 1 output 0 1 1 0 0 1 1 *
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Appendix B Internal I/O Register TIOR5—Timer I/O Control Register 5 Bit : Initial value : R/W : H'FEA2 TPU5 7 6 5 4 3 2 1 0 IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W TGR5A I/O Control 0 0 0 1 1 0 1 1 * 0 1 0 TGR5A is Output disabled 1 output Initial output is 0 compare output 0 register 1 0 Output disabled 1 Initial output is 1 output 0 0 out
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Appendix B Internal I/O Register TIOR0H—Timer I/O Control Register 0H Bit : Initial value : R/W : H'FF12 TPU0 7 6 5 4 3 2 1 0 IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W TGR0A I/O Control 0 0 0 1 1 0 1 0 TGR0A is Output disabled 1 output Initial output is 0 compare output 0 register 1 0 Output disabled 1 Initial output is 1 output 0 1 1 0 0 1 1 *
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Appendix B Internal I/O Register TIOR1—Timer I/O Control Register 1 Bit : Initial value : R/W : H'FF22 TPU1 7 6 5 4 3 2 1 0 IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W TGR1A I/O Control 0 0 0 1 1 0 1 0 TGR1A is Output disabled 1 output Initial output is 0 compare output 0 register 1 0 Output disabled 1 Initial output is 1 output 0 1 1 0 0 1 1
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Appendix B Internal I/O Register TIOR2—Timer I/O Control Register 2 Bit : Initial value : R/W : H'FF32 TPU2 7 6 5 4 3 2 1 0 IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W TGR2A I/O Control 0 0 0 1 1 0 1 1 * 0 1 0 TGR2A is Output disabled 1 output Initial output is 0 compare output 0 register 1 0 Output disabled 1 Initial output is 1 output 0 0 output
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Appendix B Internal I/O Register TIOR3L—Timer I/O Control Register 3L Bit : Initial value : R/W : H'FE83 TPU3 7 6 5 4 3 2 1 0 IOD3 IOD2 IOD1 IOD0 IOC3 IOC2 IOC1 IOC0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W TGR3C I/O Control 0 0 0 1 1 0 1 0 TGR3C is Output disabled 1 output Initial output is 0 compare 0 register*1 output 1 0 Output disabled 1 Initial output is 1 output 0 1 1 0 0 1
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Appendix B Internal I/O Register TIOR0L—Timer I/O Control Register 0L Bit : Initial value : R/W : H'FF13 TPU0 7 6 5 4 3 2 1 0 IOD3 IOD2 IOD1 IOD0 IOC3 IOC2 IOC1 IOC0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W TGR0C I/O Control 0 0 0 1 1 0 1 0 TGR0C is Output disabled 1 output Initial output is 0 compare 0 register*1 output 1 0 Output disabled 1 Initial output is 1 output 0 1 1 0 0 1 1
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Appendix B Internal I/O Register TIER3—Timer Interrupt Enable Register 3 TIER0—Timer Interrupt Enable Register 0 H'FE84 H'FF14 TPU3 TPU0 Channel 0: TIER0 Channel 3: TIER3 Bit : Initial value : R/W : 7 6 5 4 3 2 1 0 TTGE — — TCIEV TGIED TGIEC TGIEB TGIEA 0 1 0 0 0 0 0 0 R/W — — R/W R/W R/W R/W R/W Overflow interrupt enable 0 TCFV interrupt request (TCIV) disabled.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Appendix B Internal I/O Register TSR3—Timer Status Register 3 TSR0—Timer Status Register 0 H'FE85 H'FF15 TPU3 TPU0 Channel 0: TSR0 Channel 3: TSR3 : Bit 7 6 5 4 3 2 1 0 — — — TCFV TGFD TGFC TGFB TGFA Initial value : 1 1 0 0 0 0 0 0 : — — — R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/W Overflow flag 0 [Clearing condition] Writing 0 to TCFV after reading TCFV=1.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Appendix B Internal I/O Register Bit TPU3 (Up Counter) TPU4 (Up/Down Counter*) TPU5 (Up/Down Counter*) TPU0 (Up Counter) TPU1 (Up/Down Counter*) TPU2 (Up/Down Counter*) H'FE86 H'FE96 H'FEA6 H'FF16 H'FF26 H'FF36 TCNT3—Timer Counter 3 TCNT4—Timer Counter 4 TCNT5—Timer Counter 5 TCNT0—Timer Counter 0 TCNT1—Timer Counter 1 TCNT2—Timer Counter 2 : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value : 0 0 0 0 0 0 0
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Appendix B Internal I/O Register Bit : 15 Initial value : R/W Page 1292 of 1434 1 TPU3 TPU3 TPU3 TPU3 TPU4 TPU4 TPU5 TPU5 TPU0 TPU0 TPU0 TPU0 TPU1 TPU1 TPU2 TPU2 H'FE88 H'FE8A H'FE8C H'FE8E H'FE98 H'FE9A H'FEA8 H'FEAA H'FF18 H'FF1A H'FF1C H'FF1E H'FF28 H'FF2A H'FF38 H'FF3A TGR3A—Timer General Register 3A TGR3B—Timer General Register 3B TGR3C—Timer General Register 3C TGR3D—Timer General Register 3D TGR4A—Timer General Register 4A TGR
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Appendix B Internal I/O Register TPU4 TPU5 TPU1 TPU2 H'FE90 H'FEA0 H'FF20 H'FF30 TCR4—Timer Control Register 4 TCR5—Timer Control Register 5 TCR1—Timer Control Register 1 TCR2—Timer Control Register 2 Channel 1: TCR1 Channel 2: TCR2 Channel 4: TCR4 Channel 5: TCR5 Bit : 7 6 5 — CCLR1 CCLR0 4 3 CKEG1 CKEG0 2 1 0 TPSC2 TPSC1 TPSC0 Initial value : 0 0 0 0 0 0 0 0 R/W — R/W R/W R/W R/W R/W R/W R/W : Time
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Appendix B Internal I/O Register TPU4 TPU5 TPU1 TPU2 H'FE91 H'FEA1 H'FF21 H'FF31 TMDR4—Timer Mode Register 4 TMDR5—Timer Mode Register 5 TMDR1—Timer Mode Register 1 TMDR2—Timer Mode Register 2 Channel 1: TMDR1 Channel 2: TMDR2 Channel 4: TMDR4 Channel 5: TMDR5 Bit : 7 6 5 4 3 2 1 0 — — — — MD3 MD2 MD1 MD0 Initial value : 1 1 0 0 0 0 0 0 R/W — — — — R/W R/W R/W R/W MD3*1 MD2*2 MD1 MD0 0 0 0 0 Nor
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Appendix B Internal I/O Register TPU4 TPU5 TPU1 TPU2 H'FE94 H'FEA4 H'FF24 H'FF34 TIER4—Timer Interrupt Enable Register 4 TIER5—Timer Interrupt Enable Register 5 TIER1—Timer Interrupt Enable Register 1 TIER2—Timer Interrupt Enable Register 2 Channel 1: TIER1 Channel 2: TIER2 Channel 4: TIER4 Channel 5: TIER5 Bit : Initial value : R/W : 7 6 5 4 3 2 1 0 TTGE — TCIEU TCIEV — — TGIEB TGIEA 0 1 0 0 0 0 0 0 R/W —
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Appendix B Internal I/O Register TPU4 TPU5 TPU1 TPU2 H'FE95 H'FEA5 H'FF25 H'FF35 TSR4—Timer Status Register 4 TSR5—Timer Status Register 5 TSR1—Timer Status Register 1 TSR2—Timer Status Register 2 Channel 1: TSR1 Channel 2: TSR2 Channel 4: TSR4 Channel 5: TSR5 Bit : 7 6 5 4 3 2 1 0 TCFD — TCFU TCFV — — TGFB TGFA 0 0 0 0 Initial value : 1 1 R/W R — : R/(W)*1 R/(W)*1 0 0 — — R/(W)*1 R/(W)*1 Underflow flag
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Appendix B Internal I/O Register TSTR—Timer Start Register Bit : H'FEB0 TPU Common 7 6 5 4 3 2 1 0 — — CST5 CST4 CST3 CST2 CST1 CST0 Initial value : 0 0 0 0 0 0 0 0 R/W — — R/W R/W R/W R/W R/W R/W : Counter start 5 to 0 0 TCNTn counting operation disabled. 1 TCNTn counting operation enabled.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Appendix B Internal I/O Register Bit : Interrupt Controller H'FEC0 H'FEC1 H'FEC2 H'FEC3 H'FEC4 H'FEC5 H'FEC6 H'FEC7 H'FEC8 H'FEC9 H'FECA H'FECB H'FECE IPRA—Interrupt Priority Register A IPRB—Interrupt Priority Register B IPRC—Interrupt Priority Register C IPRD—Interrupt Priority Register D IPRE—Interrupt Priority Register E IPRF—Interrupt Priority Register F IPRG—Interrupt Priority Register G IPRH—Interrupt Priority Register H IPRI—Inte
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Appendix B Internal I/O Register ABWCR—Bus Width Control Register Bit : H'FED0 Bus Controller 7 6 5 4 3 2 1 0 ABW7 ABW6 ABW5 ABW4 ABW3 ABW2 ABW1 ABW0 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W Modes 5 to 7 : Initial value : R/W : Mode 4 Initial value : R/W : 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Area 7 to 0 bus width control 0 Sets area n to 16-bit access.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Appendix B Internal I/O Register WCRH—Wait Control Register H Bit : Initial value : R/W : H'FED2 Bus Controller 7 6 5 4 3 2 1 0 W71 W70 W61 W60 W51 W50 W41 W40 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W Area 6 wait control 1, 0 W61 W60 0 1 0 No program wait inserted when accessing external area of area 6. 1 1 program wait state inserted when accessing external area of area 6.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Appendix B Internal I/O Register WCRL—Wait Control Register Bit : : Bus Controller 7 6 5 4 3 2 1 0 W31 W30 W21 W20 W11 W10 W01 W00 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W Initial value : R/W H'FED3 Area 2 wait control W21 W20 0 0 No program wait inserted when accessing external area of area 2. 1 1 program wait state inserted when accessing external area of area 2.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Appendix B Internal I/O Register BCRH—Bus Control Register H Bit : Initial value : R/W : 7 H'FED4 6 5 4 Bus Controller 2 1 0 RMTS2*1 RMTS1*1 RMTS0*1 3 ICIS1 ICIS0 1 1 0 1 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W BRSTRM BRSTS1 BRSTS0 Burst cycle select 1 0 Burst cycle = 1 state. 1 Burst cycle = 2 states. Burst ROM enable 0 Area 0 is basic bus interface. (Initial value) 1 Area 0 is burst ROM interface.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Appendix B Internal I/O Register BCRL—Bus Control Register L Bit : 7 H'FED5 6 BRLE BREQOE Initial value : R/W : Bus Controller 5 4 3 2 1 0 RCTS* WDBE WAITE — OES* DDS* 0 0 0 0 1 0 0 0 R/W R/W — R/W R/W R/W R/W R/W OE select 0 CS3 pin used as port or as CS3 signal output. 1 When only area 2 is set as DRAM, or when areas 2 to 5 are set as contiguous DRAM space, the CS3 pin is used as the OE pin.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Appendix B Internal I/O Register MCR—Memory Control Register H'FED6 Bus Controller (This function is not available in the H8S/2695.) Bit : Initial value : R/W : 7 6 5 4 3 2 1 0 TPC BE RCDM CW2 MXC1 MXC0 RLW1 RLW0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Reserved bit RAS down mode 0 DRAM interface: RAS up mode selected. 1 DRAM interface: RAS down mode selected.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Appendix B Internal I/O Register DRAMCR—DRAM Control Register H'FED7 Bus Controller (This function is not available in the H8S/2695.) Bit : Initial value : R/W : 7 6 5 4 3 2 1 0 RFSHE CBRM RMODE CMF CMIE CKS2 CKS1 CKS0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Refresh mode 0 Do not perform self-refresh in software standby mode. 1 Perform self-refresh in software standby mode.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Appendix B Internal I/O Register RTCNT—Refresh Timer Counter H'FED8 Bus Controller (This function is not available in the H8S/2695.) Bit : 7 6 5 4 3 2 1 0 Initial value : 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W : RTCOR—Refresh Time Constant Register H'FED9 Bus Controller (This function is not available in the H8S/2695.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Appendix B Internal I/O Register MAR0AH—Memory Address Register 0AH MAR0AL—Memory Address Register 0AL H'FEE0 H'FEE2 DMAC DMAC Bit : 31 30 29 28 27 26 25 24 MAR : — — — — — — — — Initial value : 0 0 0 0 0 0 0 0 R/W : — — — — — — — — R/W R/W R/W R/W R/W R/W R/W R/W Bit : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MAR : * * * * * * * * * * * * * * * * Initial value : R
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Appendix B Internal I/O Register ETCR0A—Transfer Count Register 0A Bit : ETCR0A : Initial value : R/W : H'FEE6 DMAC 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 * * * * * * * * * * * * * * * * R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Sequential mode and idle mode Normal mode Transfer counter Repeat mode Holds number of transfers Transfer counter Holds block size Block size count
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Appendix B Internal I/O Register IOAR0B—I/O Address Register 0B IOAR1B—I/O Address Register 1B Bit : IOAR0B : Initial value : H'FEEC H'FEFC DMAC DMAC 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 * * * * * * * * * * * * * * * * : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W In short address mode: Specifies transfer destination/transfer source address In full address mode: Not used *
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Appendix B Internal I/O Register MAR1AH—Memory Address Register 1AH MAR1AL—Memory Address Register 1AL H'FEF0 H'FEF2 DMAC DMAC Bit : 31 30 29 28 27 26 25 24 MAR1AH : — — — — — — — — Initial value : 0 0 0 0 0 0 0 0 R/W : — — — — — — — — R/W R/W R/W R/W R/W R/W R/W R/W Bit : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MAR1AL : * * * * * * * * * * * * * * * * Initial value
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Appendix B Internal I/O Register MAR1BH—Memory Address Register 1BH MAR1BL—Memory Address Register 1BL H'FEF8 H'FEFA DMAC DMAC Bit : 31 30 29 28 27 26 25 24 MAR1BH : — — — — — — — — Initial value : 0 0 0 0 0 0 0 0 R/W : — — — — — — — — R/W R/W R/W R/W R/W R/W R/W R/W Bit : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MAR1BL : * * * * * * * * * * * * * * * * Initial val
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Appendix B Internal I/O Register P1DR—Port 1 Data Register Bit : Initial value : R/W : H'FF00 7 6 5 4 3 2 1 0 P17DR P16DR P15DR P14DR P13DR P12DR P11DR P10DR 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W P3DR—Port 3 Data Register Bit : Initial value : R/W : H'FF02 : Initial value : R/W : 6 5 4 3 2 1 0 P37DR P36DR P35DR P34DR P33DR P32DR P31DR P30DR 0 0 0 0 0 0 0 0 R/W R/
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Appendix B Internal I/O Register PCDR—Port C Data Register Bit : Initial value : R/W : H'FF0B 7 6 5 4 3 2 1 0 PC7DR PC6DR PC5DR PC4DR PC3DR PC2DR PC1DR PC0DR 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W PDDR—Port D Data Register Bit : Initial value : R/W : H'FF0C : Initial value : R/W : 6 5 4 3 2 1 0 PD7DR PD6DR PD5DR PD4DR PD3DR PD2DR PD1DR PD0DR 0 0 0 0 0 0 0 0 R/W
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Appendix B Internal I/O Register DMAWER—DMA Write Enable Register H'FF60 DMAC (This function is not available in the H8S/2695.) Bit : 7 6 5 4 3 2 1 0 DMAWER : — — — — WE1B WE1A WE0B WE0A Initial value : 0 0 0 0 0 0 0 0 R/W — — — — R/W R/W R/W R/W : Write enable 1B 0 Disables writing to all DMACR1B bits, DMABCR bits 11, 7, and 3, and DMATCR bit 5.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Appendix B Internal I/O Register DMAC DMAC DMAC DMAC H'FF62 H'FF63 H'FF64 H'FF65 DMACR0A—DMA Control Register 0A DMACR0B—DMA Control Register 0B DMACR1A—DMA Control Register 1A DMACR1B—DMA Control Register 1B (These functions are not available in the H8S/2695.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Appendix B Internal I/O Register Full address mode Bit : 7 6 5 4 3 2 1 0 DMACRB : — DAID DAIDE — DTF3 DTF2 DTF1 DTF0 Initial value : 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W : Data Transfer Factor DTF3 DTF2 DTF1 DTF0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 Block Transfer Mode (initial value) Normal Mode 0 — 1 Activated by A/D converter conversion end interrupt — 0 Activated by DREQ
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Appendix B Internal I/O Register Short address mode Bit 7 6 5 4 3 2 1 0 DTSZ DTID RPE DTDIR DTF3 DTF2 DTF1 DTF0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W DMACR Data Transfer Factor Channel A 0 Data Transfer Size 0 Byte-size transfer 1 Word-size transfer 0 0 1 1 0 — 1 Activated by A/D converter conversion end interrupt 0 — Activated by DREQ pin falling edge
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Appendix B Internal I/O Register DMABCR—DMA Band Control Register H'FF66 DMAC (This function is not available in the H8S/2695.) Short address mode Bit : DMABCRH : 15 14 13 12 11 10 9 8 FAE1 FAE0 SAE1 SAE0 DTA1B DTA1A DTA0B DTA0A Initial value : R/W : 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Data transfer acknowledge 1B Single address enable 0 0 Transfer in dual address mode.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Appendix B Internal I/O Register Full address mode 15 14 13 12 11 10 9 8 DMABCRH : FAE1 FAE0 — — DTA1 — DTA0 — Initial value : 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Bit R/W : : Data transfer acknowledge 0 0 Clearing of selected internal interrupt source at time of DMA transfer is disabled 1 Clearing of selected internal interrupt source at time of DMA transfer is enabled Data transfer ackno
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Appendix B Internal I/O Register Bit : DMABCRL : Initial value : R/W : 7 6 5 4 DTME1 DTE1 DTME0 DTE0 3 2 1 DTIE1B DTIE1A 0 DTIE0B DTIE0A 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Data transfer end interrupt enable 0A 0 Transfer end interrupt disabled 1 Transfer end interrupt enabled Data transfer end interrupt enable 1A 0 Transfer end interrupt disabled 1 Transfer end interrupt enabled Data transfer i
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Appendix B Internal I/O Register TCSR0—Timer Control/Status Register 0 Bit : Initial value : R/W : H'FF74 (W), H'FF74 (R) WDT0 7 6 5 4 3 2 1 0 OVF WT/IT TME — — CKS2 CKS1 CKS0 0 0 0 1 1 0 0 0 R/(W)* R/W R/W — — R/W R/W R/W Clock select 2 to 0 WDT0 input clock select CKS2 CKS1 CKS0 Clock Overflow cycle* (when ø= 25MHz) 0 0 0 ø/2 20.4 µs 1 ø/64 652.8 µs 1 0 ø/128 1.3 ms 1 ø/512 5.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Appendix B Internal I/O Register TCNT0—Timer Counter 0 TCNT1—Timer Counter 1 H'FF74 (W), H'FF75 (R) H'FFA2 (W), H'FFA3 (R) WDT0 WDT1 (These functions are not available in the H8S/2695.) Bit : 7 6 5 4 3 2 1 0 Initial value : 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W : Note: TCNT is write-protected by a password to prevent accidental overwriting. For details see section 15.2.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Appendix B Internal I/O Register 2 ICCR0—I C Bus Control Register 2 ICCR1—I C Bus Control Register H'FF78 H'FF80 IIC0 IIC1 (These functions are not available in the H8S/2695.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Appendix B Internal I/O Register 2 ICSR0—I C Bus Status Register 2 ICSR1—I C Bus Status Register H'FF79 H'FF81 IIC0 IIC1 (These functions are not available in the H8S/2695.) Bit : Initial value : R/W : 7 6 5 4 3 2 1 0 ESTP STOP IRTR AASX AL AAS ADZ ACKB 0 0 0 0 0 0 0 0 R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/W Acknowledge bit 0 1 When receiving, 0 is output at acknowledge output timing.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Appendix B Internal I/O Register 2 ICDR0—I C Bus Data Register 2 ICDR1—I C Bus Data Register H'FF7E H'FF86 IIC0 IIC1 (These functions are not available in the H8S/2695.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Appendix B Internal I/O Register 2 ICMR0—I C Bus Mode Register 2 ICMR1—I C Bus Mode Register H'FF7F H'FF87 IIC0 IIC1 (These functions are not available in the H8S/2695.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Appendix B Internal I/O Register SAR0—Slave Address Register SAR1—Slave Address Register H'FF7F H'FF87 IIC0 IIC1 (These functions are not available in the H8S/2695.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Appendix B Internal I/O Register ADCSR—A/D Control/Status Register Bit : Initial value : R/W : H'FF98 A/D 7 6 5 4 3 2 1 0 ADF ADIE ADST SCAN CH3 CH2 CH1 CH0 0 0 0 0 0 0 0 0 R/(W)* R/W R/W R/W R/W R/W R/W R/W Channel select 3 0 AN8 to AN11 set as group 0 analog input pins, and AN12 to AN15 as group 1 analog input pins.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Appendix B Internal I/O Register ADCR—A/D Control Register Bit : Initial value : R/W : H'FF99 A/D 7 6 5 4 3 2 1 0 TRGS1 TRGS0 — — CKS1 CKS0 — — 0 0 1 1 0 0 1 1 R/W R/W — — R/W R/W — — Clock select 1, 0 CKS1 CKS0 Description 0 0 Conversion time= 530 states (Max.) Conversion time= 266 states (Max.) 1 Conversion time= 134 states (Max.) 1 0 1 Conversion time= 68 states (Max.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Appendix B Internal I/O Register TCSR1—Timer Control/Status Register 1 H'FFA2 (W), H'FFA2 (R) WDT1 (This function is not available in the H8S/2695.) Bit : Initial value : R/W : 7 6 5 4 3 2 1 0 OVF WT/IT TME PSS RST/NMI CKS2 CKS1 CKS0 0 0 0 0 0 0 0 0 R/(W)* R/W R/W R/W R/W R/W R/W R/W Clock select 2 to 0 PSS CSK2 CSK1 CSK0 Clock Overflow cycle* (when ø= 25MHz) (when øSUB=32.768kHz) 0 0 0 0 ø/2 20.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Appendix B Internal I/O Register FLMCR1—Flash Memory Control Register 1 Bit : Initial value : R/W : H'FFA8 FLASH 7 6 5 4 3 2 1 0 FWE SWE1 ESU1 PSU1 EV1 PV1 E1 P1 —* 0 0 0 0 0 0 0 R R/W R/W R/W R/W R/W R/W R/W Program 1 0 1 Exits program mode. Enters program mode. [Setting condition] When FWE=1, SWE1=1, and PSU1=1. Erase 1 0 1 Exits erase mode. Enters erase mode.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Appendix B Internal I/O Register FLMCR2—Flash Memory Control Register 2 Bit : H'FFA9 FLASH 7 6 5 4 3 2 1 0 FLER — — — — — — — Initial value : 0 0 0 0 0 0 0 0 R/W R — — — — — — — : Flash memory error 0 1 Flash memory operating normally. Flash memory protection against writing and erasing (error protection) is ignored. [Clearing condition] At a power-on reset and in hardware standby mode.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Appendix B Internal I/O Register FLPWCR—Flash Memory Power Control Register Bit : FLASH 7 6 5 4 3 2 1 0 PDWND — — — — — — — 0 0 0 0 0 0 0 0 R/W R R R R R R R Initial value : R/W H'FFAC : Power-down disable 0 1 Transition to flash memory power-down mode enabled Transition to flash memory power-down mode disabled PORT1—Port 1 Register Bit : Initial value : R/W : H'FFB0 Port 7 6 5 4 3 2 1
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Appendix B Internal I/O Register PORT4—Port 4 Register Bit : Initial value : R/W : H'FFB3 Port 7 6 5 4 3 2 1 0 P47 P46 P45 P44 P43 P42 P41 P40 —* —* —* —* —* —* —* —* R R R R R R R R Note: * Determined by status of pins P47 to P40.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Appendix B Internal I/O Register PORTA—Port A Register Bit : H'FFB9 Port 7 6 5 4 3 2 1 0 — — — — PA3 PA2 PA1 PA0 Initial value : Undefined Undefined Undefined Undefined —* —* —* —* R/W R R R R : — — — — Note: * Determined by status of pins PA3 to PA0.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Appendix B Internal I/O Register PORTE—Port E Register Bit : H'FFBD Port 7 6 5 4 3 2 1 0 PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0 Initial value : —* —* —* —* —* —* —* —* R/W R R R R R R R R : Note: * Determined by status of pins PE7 to PE0.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Appendix C I/O Port Block Diagrams Appendix C I/O Port Block Diagrams C.1 to C.12 are I/O port block diagrams for the H8S/2633, H8S/2632, H8S/2631, H8S/2633F, and H8S/2633R. C.13 to C.24 are I/O port block diagrams for the H8S/2695. C.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Appendix C I/O Port Block Diagrams WDDR1 Reset R Q D P1nDR C P1n * WDR1 Internal address bus R Q D P1nDDR C Internal data bus Reset System controller Address output enable PPG module Pulse output enable Pulse output TPU module Output compare output/ PWM output enable Output compare output/ PWM output Internal address bus RDR1 RPOR1 Input capture input External clock input Legend: WDDR1: WDR1: RDR1: RPOR1: n = 2 or 3 Write to P1D
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Appendix C I/O Port Block Diagrams R Q D P14DDR C WDDR1 Reset P14 * R Q D P14DR C WDR1 Internal data bus Reset PPG module Pulse output enable Pulse output TPU module Output compare output/ PWM output enable Output compare output/ PWM output RDR1 RPOR1 Input capture input Interrupt controller IRQ0 interrupt input Legend: WDDR1: WDR1: RDR1: RPOR1: Write to P1DDR Write to P1DR Read P1DR Read port 1 Note: * Priority order: output
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Appendix C I/O Port Block Diagrams R Q D P15DDR C WDDR1 Reset Internal data bus Reset R Q D P15DR C P15 * WDR1 PPG module Pulse output enable Pulse output TPU module Output compare output/ PWM output enable Output compare output/ PWM output RDR1 RPOR1 Input capture input External clock input Legend: WDDR1: WDR1: RDR1: RPOR1: Write to P1DDR Write to P1DR Read P1DR Read port 1 Note: * Priority order: output compare output/PWM outpu
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Appendix C I/O Port Block Diagrams R Q D P16DDR C WDDR1 Reset R Q D P16DR C P16 * Internal data bus Reset WDR1 PWM module PWM2 output enable PWM2 output PPG module Pulse output enable Pulse output RDR1 TPU module Output compare output/ PWM output enable Output compare output/ PWM output RPOR1 Input capture input Input controller IRQ1 interrupt input Legend WDDR1: WDR1: RDR1: RPOR1: Write to P1DDR Write to P1DR Read P1DR Read po
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Appendix C I/O Port Block Diagrams R Q D P17DDR C WDDR1 Reset R Q D P17DR C P17 * Internal data bus Reset WDR1 PWM module PWM3 output enable PWM3 output PPG module Pulse output enable Pulse output TPU module Output compare output/ PWM output enable Output compare output/ PWM output RDR1 RPOR1 Input capture input External clock input Legend: WDDR1: WDR1: RDR1: RPOR1: Write to P1DDR Write to P1DR Read P1DR Read port 1 Note: * Prior
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 C.2 Appendix C I/O Port Block Diagrams Port 3 Block Diagram R Q D P30DDR C WDDR3 *1 REset R Q D P30DR C P30 Internal data bus Reset WDR3 Reset *2 R Q D P30ODR C WODR3 RODR3 SCI module Serial transmit enable Serial transmit data TxD0/IrTxD RDR3 RPOR3 Legend: WDDR3: WDR3: WODR3: RDR3: RPOR3: RODR3: Write to P3DDR Write to P3DR Write to P3ODR Read P3DR Read port 3 Read P3ODR Notes: 1. Output enable signal 2.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Appendix C I/O Port Block Diagrams Reset R Q D P31DDR C Reset R Q D P31DR C P31 WDR3 *2 Internal data bus WDDR3 *1 Reset R Q D P31ODR C WODR3 RODR3 SCI module RDR3 Serial receive data enable RPOR3 Serial receive data RxD0/IrRxD Legend: WDDR3: WDR3: WODR3: RDR3: RPOR3: RODR3: Write to P3DDR Write to P3DR Write to P3ODR Read P3DR Read port 3 Read P3ODR Notes: 1. Output enable signal 2. Open drain control signal Figure C.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Appendix C I/O Port Block Diagrams R Q D P32DDR C WDDR3 *2 Reset Internal data bus Reset R Q D P32DR C P32 *1 WDR3 Reset *3 R Q D P32ODR C WODR3 IIC1 module SDA1 output IIC1 output enable RODR3 SDA1 input SCI module Serial clock output enable Serial clock output RDR3 Serial clock input enable RPOR3 Serial clock input Interrupt controller IRQ4 interrupt input Legend: WDDR3: WDR3: WODR3: RDR3: RPOR3: RODR3: Write to P3D
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Appendix C I/O Port Block Diagrams R Q D P33DDR C WDDR3 *1 Reset R Q D P33DR C P33 Internal data bus Reset WDR3 Reset *2 R Q D P33ODR C WODR3 RODR3 SCI module Serial transmit enable Serial transmit data TxD1 RDR3 RPOR3 IIC1 module SCL1 output IIC1 output enable SCL1 input Legend: WDDR3: WDR3: WODR3: RDR3: RPOR3: RODR3: Write to P3DDR Write to P3DR Write to P3ODR Read P3DR Read port 3 Read P3ODR Notes: 1. Output enable signal 2.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Appendix C I/O Port Block Diagrams Reset R Q D P34DDR C Reset *3 P34 R Q D P34DR C WDR3 *2 Internal data bus WDDR3 *1 Reset R Q D P34ODR C WODR3 RODR3 SCI module RDR3 Serial receive data enable RPOR3 Serial receive data RxD1 IIC0 module SDA0 output IIC0 output enable SDA0 Input Legend: WDDR3: WDR3: WODR3: RDR3: RPOR3: RODR3: Write to P3DDR Write to P3DR Write to P3ODR Read P3DR Read port 3 Read P3ODR Notes: 1.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Appendix C I/O Port Block Diagrams Reset R Q D P35DDR C Reset R Q D P35DR C P35 *1 WDR3 Internal data bus WDDR3 *2 Reset *3 R Q D P35ODR C WODR3 RODR3 SCI module Serial clock output enable Serial clock output RDR3 Serial clock input enable RPOR3 Serial clock input IIC0 module SCL0 output IIC0 output enable SCL0 input Interrupt controller IRQ5 interrupt input Legend: WDDR3: WDR3: WODR3: RDR3: RPOR3: RODR3: Write to P3DDR Writ
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Appendix C I/O Port Block Diagrams Reset R Q D P36DDR C Reset R Q D P36DR C P36 WDR3 *2 Internal data bus WDDR3 *1 Reset R Q D P36ODR C WODR3 RODR3 SCI module RDR3 Serial receive data enable RPOR3 Serial receive data RxD4 Legend: WDDR3: WDR3: WODR3: RDR3: RPOR3: RODR3: Write to P3DDR Write to P3DR Write to P3ODR Read P3DR Read port 3 Read P3ODR Notes: 1. Output enable signal 2. Open drain control signal Figure C.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Appendix C I/O Port Block Diagrams Reset R Q D P37DDR C Reset R Q D P37DR C P37 WDR3 Internal data bus WDDR3 *1 Reset *2 R Q D P37ODR C WODR3 RODR3 SCI module Serial transmit enable Serial transmit data RDR3 TxD4 RPOR3 Legend: WDDR3: WDR3: WODR3: RDR3: RPOR3: RODR3: Write to P3DDR Write to P3DR Write to P3ODR Read P3DR Read port 3 Read P3ODR Notes: 1. Output enable signal 2. Open drain control signal Figure C.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Port 4 Block Diagram RPOR4 P4n Internal data bus C.3 Appendix C I/O Port Block Diagrams A/D converter module Analog input Legend: RPOR4: Read port 4 n = 0 to 5 RPOR4 P4n Internal data bus Figure C.3 (a) Port 4 Block Diagram (Pins P40 to P45) A/D converter module Analog input D/A converter module Output enable Analog output Legend: RPOR4: Read port 4 n = 6 or 7 Figure C.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Appendix C I/O Port Block Diagrams C.4 Port 7 Block Diagram R Q D P7nDDR C WDDR7 Mode 7 P7n Modes 4 to 6 Reset R Q D P7nDR C WDR7 Internal data bus Reset Bus controller Chip select RDR7 RPOR7 DMA controller DMA request input 8-bit timer Legend: WDDR7: Write to P7DDR WDR7: Write to P7DR RDR7: Read P7DR RPOR7: Read port 7 n = 0 or 1 Reset/Count input Figure C.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Appendix C I/O Port Block Diagrams R Q D P72DDR C WDDR7 Mode 7 * P72 Modes 4 to 6 Reset R Q D P72DR C WDR7 Internal data bus Reset Bus controller Chip select DMA controller DMA transfer end enable DMA transferred RDR7 8-bit timer Timer output TMO0 Timer output enable RPOR7 Legend: WDDR7: WDR7: RDR7: RPOR7: Write to P7DDR Write to P7DR Read P7DR Read port 7 Note: * Priority order: (Mode 7) DMA transfer end output > 8-bit timer
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Appendix C I/O Port Block Diagrams R Q D P73DDR C WDDR7 Mode 7 * P73 Modes 4 to 6 Reset R Q D P73DR C WDR7 Internal data bus Reset Bus controller Chip select DMA controller DMA transfer end enable DMA transfer end RDR7 RPOR7 8-bit timer Timer output TMO1 Timer output enable Legend: WDDR7: WDR7: RDR7: RPOR7: Write to P7DDR Write to P7DR Read P7DR Read port 7 Note: * Priority order: (Mode 7) DMA transfer end output > 8-bit timer ou
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Appendix C I/O Port Block Diagrams R Q D P74DDR C WDDR7 Reset R Q D P74DR C P74 Internal data bus Reset WDR7 8-bit timer 8-bit timer output enable 8-bit timer output RDR7 RPOR7 System controller Manual reset input enable Manual reset input Legend: WDDR7: WDR7: RDR7: RPOR7: Write to P7DDR Write to P7DR Read P7DR Read port 7 Figure C.4 (d) Port 7 Block Diagram (Pin P74) R01UH0166EJ0600 Rev. 6.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Appendix C I/O Port Block Diagrams R Q D P75DDR C WDDR7 Reset P75 * R Q D P75DR C Internal data bus Reset WDR7 8-bit timer Timer output enable Timer output SCI module Serial clock output enable Serial clock RDR7 Serial clock input enable RPOR7 Serial clock input Legend: WDDR7: WDR7: RDR7: RPOR7: Write to P7DDR Write to P7DR Read P7DR Read port 7 Note: * Priority order: Serial clock output > 8-bit timer output > DR output Figu
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Appendix C I/O Port Block Diagrams R Q D P76DDR C WDDR7 Reset R Q D P76DR C P76 Internal data bus Reset WDR7 SCI module RDR7 Serial receive data enable RPOR7 Serial receive data RxD3 Legend: WDDR7: WDR7: RDR7: RPOR7: Write to P7DDR Write to P7DR Read P7DR Read port 7 Figure C.4 (f) Port 7 Block Diagram (Pin P76) R01UH0166EJ0600 Rev. 6.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Appendix C I/O Port Block Diagrams R Q D P77DDR C WDDR7 Reset R Q D P77DR C P77 Internal data bus Reset WDR7 SCI module Serial transmit enable data Serial transmit data TxD3 RDR7 RPOR7 Legend: WDDR7: WDR7: RDR7: RPOR7: Write to P7DDR Write to P7DR Read P7DR Read port 7 Figure C.4 (g) Port 7 Block Diagram (Pin P77) Page 1358 of 1434 R01UH0166EJ0600 Rev. 6.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Port 9 Block Diagram RPOR9 P9n Internal data bus C.5 Appendix C I/O Port Block Diagrams A/D converter module Analog input Legend: RPOR9: Read port 9 n = 0 to 5 RPOR9 P9n Internal data bus Figure C.5 (a) Port 9 Block Diagram (Pins P90 to P95) A/D converter module Analog input D/A converter module Output enable Analog output Legend: RPOR9: Read port 9 n = 6 or 7 Figure C.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Appendix C I/O Port Block Diagrams C.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Appendix C I/O Port Block Diagrams WPCRA RPCRA Internal address bus R Q D PA1PCR C Internal data bus Reset Smart card mode signal TxD output TxD output enable Reset R Q D PA1DDR C WDDRA *1 Reset PA1 Modes 4 to 6 Address enable R Q D PA1DR C WDRA Reset *2 R Q D PA1ODR C WODRA RODRA RDRA RPORA Legend: WDDRA: WDRA: WODRA: WPCRA: RDRA: RPORA: RODRA: RPCRA: Write to PADDR Write to PADR Write to PAODR Write to PAPCR Read PADR
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Appendix C I/O Port Block Diagrams Reset RPCRA RxD input enable Internal data bus WPCRA Internal address bus R Q D PA2PCR C Reset R Q D PA2DDR C WDDRA *1 Reset PA2 Modes 4 to 6 Address enable R Q D PA2DR C WDRA Reset *2 R Q D PA2ODR C WODRA RODRA RDRA RxD input Legend: WDDRA: WDRA: WODRA: WPCRA: RDRA: RPORA: RODRA: RPCRA: Write to PADDR Write to PADR Write to PAODR Write to PAPCR Read PADR Read port A Read PAODR Read PAPCR
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Appendix C I/O Port Block Diagrams WPCRA RPCRA SCK input enable Internal address bus R Q D PA3PCR C Internal data bus Reset SCK output SCK output enable Reset R Q D PA3DDR C WDDRA *1 Reset PA3 Modes 4 to 6 Address enable R Q D PA3DR C WDRA Reset *2 R Q D PA3ODR C WODRA RODRA RDRA SCK input Legend: WDDRA: WDRA: WODRA: WPCRA: RDRA: RPORA: RODRA: RPCRA: Write to PADDR Write to PADR Write to PAODR Write to PAPCR Read PADR R
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Appendix C I/O Port Block Diagrams C.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 C.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Appendix C I/O Port Block Diagrams WPCRC RPCRC PWM output PWM output enable Internal address bus R Q D PCnPCR C Internal data bus Reset Reset R Q D PCnDDR C WDDRC *1 Reset Modes 4/5 Mode 6 PCn R Q D PCnDR C WDRC *2 Reset R Q D PCnODR C WODRC RODRC RDRC RPORC Legend: Notes: 1. Output enable signal 2.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 C.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Appendix C I/O Port Block Diagrams C.10 Port E Block Diagram WPCRE RPCRE Internal lower data bus R Q D PEnPCR C Internal upper data bus Reset Reset External address write R Q D PEnDDR C WDDRE Reset Mode 7 Modes 4 to 6 PEn R Q D PEnDR C WDRE RDRE RPORE External addres lower read Legend: WDDRE: WDRE: WPCRE: RDRE: RPORE: RPCRE: n = 0 to 7 Write to PEDDR Write to PEDR Write to PEPCR Read PEDR Read port E Read PEPCR Figure C.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Port F Block Diagram Reset R Q D PF0DDR C WDDRF Internal data bus C.11 Appendix C I/O Port Block Diagrams Bus controller Modes 4 to 6 BRLE bit Reset R Q D PF0DR C PF0 WDRF RDRF RPORF Bus request input Legend: WDDRF: WDRF: RDRF: RPORF: IRQ interrupt input Write to PFDDR Write to PFDR Read PFDR Read port F Figure C.11 (a) Port F Block Diagram (Pin PF0) R01UH0166EJ0600 Rev. 6.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Appendix C I/O Port Block Diagrams BUZZ output BUZZ output enable R Q D PF1DDR C WDDRF Reset R Q D PF1DR C PF1 Internal data bus Reset WDRF Modes 4 to 6 Bus controller BRLE output Bus request acknowledge output RDRF RPORF Legend: WDDRF: WDRF: RDRF: RPORF: Write to PFDDR Write to PFDR Read PFDR Read port F Figure C.11 (b) Port F Block Diagram (Pin PF1) Page 1370 of 1434 R01UH0166EJ0600 Rev. 6.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Reset R Q D PF2DDR C WDDRF Internal data bus Appendix C I/O Port Block Diagrams Reset Modes 4 to 6 PF2 Modes 4 to 6 Bus controller Wait enable R Q D PF2DR C WDRF Modes 4 to 6 Bus request output enable Bus request output RDRF RPORF Wait input LCAS output enable LCASS bit Legend: WDDRF: WDRF: RDRF: RPORF: LCAS output Write to PFDDR Write to PFDR Read PFDR Read port F Figure C.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Appendix C I/O Port Block Diagrams R Q D PF3DDR C WDDRF Reset PF3 Modes 4 to 6 R Q D PF3DR C Internal data bus Reset WDRF Bus controller LWR output RDRF RPORF ADTRG input IRQ interrupt input Legend: WDDRF: WDRF: RDRF: RPORF: Write to PFDDR Write to PFDR Read PFDR Read port F Figure C.11 (d) Port F Block Diagram (Pin PF3) Page 1372 of 1434 R01UH0166EJ0600 Rev. 6.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Appendix C I/O Port Block Diagrams R Q D PF4DDR C WDDRF Reset PF4 Modes 4 to 6 R Q D PF4DR C Internal data bus Reset WDRF Bus controller HWR output RDRF RPORF Legend: WDDRF: WDRF: RDRF: RPORF: Write to PFDDR Write to PFDR Read PFDR Read port F Figure C.11 (e) Port F Block Diagram (Pin PF4) R01UH0166EJ0600 Rev. 6.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Appendix C I/O Port Block Diagrams Reset Internal data bus R Q D PF5DDR C WDDRF Reset PF5 Modes 4 to 6 R Q D PF5DR C WDRF Bus controller RD output RDRF RPORF Legend: WDDRF: WDRF: RDRF: RPORF: Write to PFDDR Write to PFDR Read PFDR Read port F Figure C.11 (f) Port F Block Diagram (Pin PF5) Page 1374 of 1434 R01UH0166EJ0600 Rev. 6.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Appendix C I/O Port Block Diagrams R Q D PF6DDR C WDDRF Reset PF6 Modes 4 to 6 R Q D PF6DR C Internal data bus Reset WDRF LCAS output LCAS output enable LCASS Bus controller AS output RDRF RPORF Legend: WDDRF: WDRF: RDRF: RPORF: Write to PFDDR Write to PFDR Read PFDR Read port F Figure C.11 (g) Port F Block Diagram (Pin PF6) R01UH0166EJ0600 Rev. 6.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Appendix C I/O Port Block Diagrams S* R Q D D PF7DDR C WDDRF Reset R Q D PF7DR C PF7 Internal data bus Modes 4 to 6 Reset WDRF ø RDRF RPORF Legend: WDDRF: WDRF: RDRF: RPORF: Note: * Set priority Write to PFDDR Write to PFDR Read PFDR Read port F Figure C.11 (h) Port F Block Diagram (Pin PF7) Page 1376 of 1434 R01UH0166EJ0600 Rev. 6.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 C.12 Appendix C I/O Port Block Diagrams Port G Block Diagram R Q D PG0DDR C WDDRG Reset R Q D PG0DR C PG0 Internal data bus Reset WDRG Modes 4 to 6 Bus controller CAS enable CAS output RDRG RPORG IRQ interrupt input Legend: WDDRG: WDRG: RDRG: RPORG: Write to PGDDR Write to PGDR Read PGDR Read port G Figure C.12 (a) Port G Block Diagram (Pin PG0) R01UH0166EJ0600 Rev. 6.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Appendix C I/O Port Block Diagrams R Q D PG1DDR C WDDRG Reset PG1 Modes 4 to 6 R Q D PG1DR C Internal data bus Reset WDRG OE output OE output enable Bus controller Chip select RDRG RPORG IRQ interrupt input Legend: WDDRG: WDRG: RDRG: RPORG: Write to PGDDR Write to PGDR Read PGDR Read port G Figure C.12 (b) Port G Block Diagram (Pin PG1) Page 1378 of 1434 R01UH0166EJ0600 Rev. 6.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Appendix C I/O Port Block Diagrams R Q D PGnDDR C WDDRG Reset PGn Modes 4 to 6 R Q D PGnDR C Internal data bus Reset WDRG Bus controller Chip select RDRG RPORG Legend: WDDRG: WDRG: RDRG: RPORG: n = 2 or 3 Write to PGDDR Write to PGDR Read PGDR Read port G Figure C.12 (c) Port G Block Diagram (Pin PG2 and PG3) R01UH0166EJ0600 Rev. 6.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Appendix C I/O Port Block Diagrams Modes 4/5 Modes 6/7 S R Q D PG4DDR C WDDRG Reset PG4 Modes 4 to 6 R Q D PG4DR C Internal data bus Reset WDRG Bus controller Chip select RDRG RPORG Legend: WDDRG: WDRG: RDRG: RPORG: Write to PGDDR Write to PGDR Read PGDR Read port G Figure C.12 (d) Port G Block Diagram (Pin PG4) Page 1380 of 1434 R01UH0166EJ0600 Rev. 6.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 C.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Appendix C I/O Port Block Diagrams WDDR1 Reset R Q D P1nDR C P1n * Internal address bus R Q D P1nDDR C Internal data bus Reset System controller*1 Address output enable WDR1 TPU module Output compare output/ PWM output enable Output compare output/ PWM output Internal address bus RDR1 RPOR1 Input capture input External clock input Legend: WDDR1: WDR1: RDR1: RPOR1: n = 2 or 3 Write to P1DDR Write to P1DR Read P1DR Read port 1
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Appendix C I/O Port Block Diagrams R Q D P14DDR C WDDR1 Reset P14 * R Q D P14DR C Internal data bus Reset WDR1 TPU module Output compare output/ PWM output enable Output compare output/ PWM output RDR1 RPOR1 Input capture input Interrupt controller IRQ0 interrupt input Legend: WDDR1: WDR1: RDR1: RPOR1: Write to P1DDR Write to P1DR Read P1DR Read port 1 Note: * Priority order: output compare output/PWM output > DR output Figu
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Appendix C I/O Port Block Diagrams R Q D P15DDR C WDDR1 Reset P15 * Internal data bus Reset R Q D P15DR C WDR1 TPU module Output compare output/ PWM output enable Output compare output/ PWM output RDR1 RPOR1 Input capture input External clock input Legend: WDDR1: WDR1: RDR1: RPOR1: Write to P1DDR Write to P1DR Read P1DR Read port 1 Note: * Priority order: output compare output/PWM output > DR output Figure C.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Appendix C I/O Port Block Diagrams R Q D P16DDR C WDDR1 Reset Internal data bus Reset R Q D P16DR C P16 * WDR1 RDR1 TPU module Output compare output/ PWM output enable Output compare output/ PWM output RPOR1 Input capture input Interrupt controller IRQ1 interrupt input Legend: WDDR1: WDR1: RDR1: RPOR1: Write to P1DDR Write to P1DR Read P1DR Read port 1 Note: * Priority order: output compare output/PWM output > DR output Figu
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Appendix C I/O Port Block Diagrams R Q D P17DDR C WDDR1 Reset R Q D P17DR C P17 * Internal data bus Reset WDR1 TPU module Output compare output/ PWM output enable Output compare output/ PWM output RDR1 RPOR1 Input capture input External clock input Legend: WDDR1: WDR1: RDR1: RPOR1: Write to P1DDR Write to P1DR Read P1DR Read port 1 Note: * Priority order: output compare output/PWM output > DR output Figure C.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 C.14 Appendix C I/O Port Block Diagrams Port 3 Block Diagram R Q D P30DDR C WDDR3 *1 Reset Internal data bus Reset R Q D P30DR C P30 WDR3 Reset *2 R Q D P30ODR C WODR3 RODR3 SCI module Serial transmit enable Serial transmit data TxD0/IrTxD RDR3 RPOR3 Legend: WDDR3: WDR3: WODR3: RDR3: RPOR3: RODR3: Write to P3DDR Write to P3DR Write to P3ODR Read P3DR Read port 3 Read P3ODR Notes: 1. Output enable signal 2.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Appendix C I/O Port Block Diagrams Reset Internal data bus R Q D P31DDR C WDDR3 *1 Reset R Q D P31DR C P31 WDR3 *2 Reset R Q D P31ODR C WODR3 RODR3 SCI module Serial receive data enable RDR3 RPOR3 Serial receive data RxD0/IrRxD Legend: WDDR3: WDR3: WODR3: RDR3: RPOR3: RODR3: Write to P3DDR Write to P3DR Write to P3ODR Read P3DR Read port 3 Read P3ODR Notes: 1. Output enable signal 2. Open drain control signal Figure C.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Appendix C I/O Port Block Diagrams R Q D P32DDR C WDDR3 *2 Reset P32 *1 R Q D P32DR C Internal data bus Reset WDR3 Reset *3 R Q D P32ODR C WODR3 RODR3 SCI module Serial clock output enable Serial clock output RDR3 Serial clock input enable RPOR3 Serial clock input Interrupt controller IRQ4 interrupt input Legend: WDDR3: WDR3: WODR3: RDR3: RPOR3: RODR3: Write to P3DDR Write to P3DR Write to P3ODR Read P3DR Read port 3 Read
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Appendix C I/O Port Block Diagrams R Q D P33DDR C WDDR3 *1 Reset Internal data bus Reset R Q D P33DR C P33 WDR3 Reset *2 R Q D P33ODR C WODR3 RODR3 SCI module Serial transmit enable Serial transmit data TxD1 RDR3 RPOR3 Legend: WDDR3: WDR3: WODR3: RDR3: RPOR3: RODR3: Write to P3DDR Write to P3DR Write to P3ODR Read P3DR Read port 3 Read P3ODR Notes: 1. Output enable signal 2. Open drain control signal Figure C.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Appendix C I/O Port Block Diagrams R Q D P34DDR C WDDR3 *1 Reset R Q D P34DR C P34 Internal data bus Reset WDR3 *2 Reset R Q D P34ODR C WODR3 RODR3 SCI module RDR3 Serial receive data enable RPOR3 Serial receive data RxD1 Legend: WDDR3: WDR3: WODR3: RDR3: RPOR3: RODR3: Write to P3DDR Write to P3DR Write to P3ODR Read P3DR Read port 3 Read P3ODR Notes: 1. Output enable signal 2. Open drain control signal Figure C.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Appendix C I/O Port Block Diagrams R Q D P35DDR C WDDR3 *2 Reset R Q D P35DR C *1 P35 Internal data bus Reset WDR3 Reset *3 R Q D P35ODR C WODR3 RODR3 SCI module Serial clock 1 output enable Serial clock 4 output enable Serial clock 1 output Serial clock 4 output RDR3 RPOR3 Serial clock 1 input Serial clock 4 input Interrupt controller IRQ5 interrupt input Legend: WDDR3: WDR3: WODR3: RDR3: RPOR3: RODR3: Write to P3DDR Write t
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Appendix C I/O Port Block Diagrams R Q D P36DDR C WDDR3 *1 Reset Internal data bus Reset R Q D P36DR C P36 WDR3 *2 Reset R Q D P36ODR C WODR3 RODR3 SCI module RDR3 Serial receive data enable RPOR3 Serial receive data RxD4 Legend: WDDR3: WDR3: WODR3: RDR3: RPOR3: RODR3: Write to P3DDR Write to P3DR Write to P3ODR Read P3DR Read port 3 Read P3ODR Notes: 1. Output enable signal 2. Open drain control signal Figure C.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Appendix C I/O Port Block Diagrams R Q D P37DDR C WDDR3 *1 Reset Internal data bus Reset R Q D P37DR C P37 WDR3 Reset *2 R Q D P37ODR C WODR3 RODR3 SCI module Serial transmit enable Serial transmit data TxD4 RDR3 RPOR3 Legend: WDDR3: WDR3: WODR3: RDR3: RPOR3: RODR3: Write to P3DDR Write to P3DR Write to P3ODR Read P3DR Read port 3 Read P3ODR Notes: 1. Output enable signal 2. Open drain control signal Figure C.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Port 4 Block Diagram RPOR4 P4n Internal data bus C.15 Appendix C I/O Port Block Diagrams A/D converter module Analog input Legend: RPOR4: Read port 4 n = 0 to 7 Figure C.15 Port 4 Block Diagram (Pins P40 to P47) R01UH0166EJ0600 Rev. 6.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Appendix C I/O Port Block Diagrams C.16 Port 7 Block Diagram Reset R Q D P7nDDR C WDDR7 Mode 7 P7n Modes 4 to 6 Reset R Q D P7nDR C WDR7 Bus controller Chip select RDR7 RPOR7 Legend: WDDR7: WDR7: RDR7: RPOR7: n = 0 to 3 Write to P7DDR Write to P7DR Read P7DR Read port 7 Figure C.16 (a) Port 7 Block Diagram (Pins P70 to P73) Page 1396 of 1434 R01UH0166EJ0600 Rev. 6.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Appendix C I/O Port Block Diagrams R Q D P74DDR C WDDR7 Reset R Q D P74DR C P74 Internal data bus Reset WDR7 RDR7 RPOR7 System controller Manual reset input enable Manual reset input Legend: WDDR7: WDR7: RDR7: RPOR7: Write to P7DDR Write to P7DR Read P7DR Read port 7 Figure C.16 (b) Port 7 Block Diagram (Pin P74) R01UH0166EJ0600 Rev. 6.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Appendix C I/O Port Block Diagrams Reset Internal data bus R Q D P75DDR C WDDR7 Reset P75 * R Q D P75DR C WDR7 SCI module Serial clock output enable Serial clock Serial clock input enable RDR7 RPOR7 Serial clock input Legend: WDDR7: WDR7: RDR7: RPOR7: Write to P7DDR Write to P7DR Read P7DR Read port 7 Note: * Priority order: Serial clock output > DR output Figure C.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Appendix C I/O Port Block Diagrams R Q D P76DDR C WDDR7 Reset Internal data bus Reset R Q D P76DR C P76 WDR7 SCI module RDR7 Serial receive data enable RPOR7 Serial receive data RxD3 Legend: WDDR7: WDR7: RDR7: RPOR7: Write to P7DDR Write to P7DR Read P7DR Read port 7 Figure C.16 (d) Port 7 Block Diagram (Pin P76) R01UH0166EJ0600 Rev. 6.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Appendix C I/O Port Block Diagrams R Q D P77DDR C WDDR7 Reset Internal data bus Reset R Q D P77DR C P77 WDR7 SCI module Serial transmit enable Serial transmit data TxD3 RDR7 RPOR7 Legend: WDDR7: WDR7: RDR7: RPOR7: Write to P7DDR Write to P7DR Read P7DR Read port 7 Figure C.16 (e) Port 7 Block Diagram (Pin P77) Page 1400 of 1434 R01UH0166EJ0600 Rev. 6.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Port 9 Block Diagram RPOR9 P9n Internal data bus C.17 Appendix C I/O Port Block Diagrams A/D converter module Analog input Legend: RPOR9: Read port 9 n = 0 to 7 Figure C.17 Port 9 Block Diagram (Pins P90 to P97) R01UH0166EJ0600 Rev. 6.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Appendix C I/O Port Block Diagrams C.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Appendix C I/O Port Block Diagrams WPCRA RPCRA Internal address bus R Q D PA1PCR C Internal data bus Reset Smart card mode signal TxD output TxD output enable Reset R Q D PA1DDR C WDDRA *1 Reset Modes 4 to 6 Address enable PA1 R Q D PA1DR C WDRA Reset *2 R Q D PA1ODR C WODRA RODRA RDRA RPORA Legend: WDDRA: WDRA: WODRA: WPCRA: RDRA: RPORA: RODRA: RPCRA: Write to PADDR Write to PADR Write to PAODR Write to PAPCR Read PADR
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Appendix C I/O Port Block Diagrams Reset RPCRA RxD input enable Internal data bus WPCRA Internal address bus R Q D PA2PCR C Reset R Q D PA2DDR C WDDRA *1 Reset PA2 Modes 4 to 6 Address enable R Q D PA2DR C WDRA Reset *2 R Q D PA2ODR C WODRA RODRA RDRA RxD input Legend: WDDRA: WDRA: WODRA: WPCRA: RDRA: RPORA: RODRA: RPCRA: Write to PADDR Write to PADR Write to PAODR Write to PAPCR Read PADR Read port A Read PAODR Read PAPCR
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Appendix C I/O Port Block Diagrams WPCRA RPCRA SCK input enable Internal address bus R Q D PA3PCR C Internal data bus Reset SCK output SCK output enable Reset R Q D PA3DDR C WDDRA *1 Reset Modes 4 to 6 Address enable PA3 R Q D PA3DR C WDRA Reset *2 R Q D PA3ODR C WODRA RODRA RDRA SCK input Legend: WDDRA: WDRA: WODRA: WPCRA: RDRA: RPORA: RODRA: RPCRA: Write to PADDR Write to PADR Write to PAODR Write to PAPCR Read PADR Re
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Appendix C I/O Port Block Diagrams C.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 C.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Appendix C I/O Port Block Diagrams C.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 C.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Appendix C I/O Port Block Diagrams Port F Block Diagram Reset R Q D PF0DDR C WDDRF Internal data bus C.23 Bus controller Modes 4 to 6 BRLE bit Reset R Q D PF0DR C PF0 WDRF RDRF RPORF Bus request input IRQ interrupt input Legend: WDDRF: WDRF: RDRF: RPORF: Write to PFDDR Write to PFDR Read PFDR Read port F Figure C.23 (a) Port F Block Diagram (Pin PF0) Page 1410 of 1434 R01UH0166EJ0600 Rev. 6.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Appendix C I/O Port Block Diagrams R Q D PF1DDR C WDDRF Reset Internal data bus Reset R Q D PF1DR C PF1 WDRF Modes 4 to 6 Bus controller BRLE output Bus request acknowledge output RDRF RPORF Legend: WDDRF: WDRF: RDRF: RPORF: Write to PFDDR Write to PFDR Read PFDR Read port F Figure C.23 (b) Port F Block Diagram (Pin PF1) R01UH0166EJ0600 Rev. 6.
Appendix C I/O Port Block Diagrams Internal data bus H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Reset R Q D PF2DDR C Bus controller Wait enable WDDRF Reset Modes 4 to 6 PF2 Modes 4 to 6 R Q D PF2DR C WDRF Modes 4 to 6 Bus request output enable Bus request output RDRF RPORF Wait input Legend: WDDRF: WDRF: RDRF: RPORF: Write to PFDDR Write to PFDR Read PFDR Read port F Figure C.23 (c) Port F Block Diagram (Pin PF2) Page 1412 of 1434 R01UH0166EJ0600 Rev. 6.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Appendix C I/O Port Block Diagrams R Q D PF3DDR C WDDRF Reset PF3 Modes 4 to 6 Internal data bus Reset R Q D PF3DR C WDRF Bus controller LWR output RDRF RPORF ADTRG input IRQ interrupt input Legend: WDDRF: WDRF: RDRF: RPORF: Write to PFDDR Write to PFDR Read PFDR Read port F Figure C.23 (d) Port F Block Diagram (Pin PF3) R01UH0166EJ0600 Rev. 6.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Appendix C I/O Port Block Diagrams Internal data bus Reset R Q D PF4DDR C WDDRF Reset PF4 Modes 4 to 6 R Q D PF4DR C WDRF Bus controller HWR output RDRF RPORF Legend: WDDRF: WDRF: RDRF: RPORF: Write to PFDDR Write to PFDR Read PFDR Read port F Figure C.23 (e) Port F Block Diagram (Pin PF4) Page 1414 of 1434 R01UH0166EJ0600 Rev. 6.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Appendix C I/O Port Block Diagrams R Q D PF5DDR C WDDRF Reset PF5 Modes 4 to 6 R Q D PF5DR C Internal data bus Reset WDRF Bus controller RD output RDRF RPORF Legend: WDDRF: WDRF: RDRF: RPORF: Write to PFDDR Write to PFDR Read PFDR Read port F Figure C.23 (f) Port F Block Diagram (Pin PF5) R01UH0166EJ0600 Rev. 6.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Appendix C I/O Port Block Diagrams Reset Internal data bus R Q D PF6DDR C WDDRF Reset PF6 Modes 4 to 6 R Q D PF6DR C WDRF Bus controller AS output RDRF RPORF Legend: WDDRF: WDRF: RDRF: RPORF: Write to PFDDR Write to PFDR Read PFDR Read port F Figure C.23 (g) Port F Block Diagram (Pin PF6) Page 1416 of 1434 R01UH0166EJ0600 Rev. 6.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Appendix C I/O Port Block Diagrams S* R Q D D PF7DDR C WDDRF Reset Internal data bus Modes 4 to 6 Reset R Q D PF7DR C PF7 WDRF φ RDRF RPORF Legend: WDDRF: WDRF: RDRF: RPORF: Note: * Set priority Write to PFDDR Write to PFDR Read PFDR Read port F Figure C.23 (h) Port F Block Diagram (Pin PF7) R01UH0166EJ0600 Rev. 6.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Appendix C I/O Port Block Diagrams C.24 Port G Block Diagram Reset Internal data bus R Q D PG0DDR C WDDRG Reset R Q D PG0DR C PG0 WDRG RDRG RPORG IRQ interrupt input Legend: WDDRG: WDRG: RDRG: RPORG: Write to PGDDR Write to PGDR Read PGDR Read port G Figure C.24 (a) Port G Block Diagram (Pin PG0) Page 1418 of 1434 R01UH0166EJ0600 Rev. 6.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Appendix C I/O Port Block Diagrams R Q D PG1DDR C WDDRG Reset PG1 Modes 4 to 6 Internal data bus Reset R Q D PG1DR C WDRG Bus controller Chip select RDRG RPORG IRQ interrupt input Legend: WDDRG: WDRG: RDRG: RPORG: Write to PGDDR Write to PGDR Read PGDR Read port G Figure C.24 (b) Port G Block Diagram (Pin PG1) R01UH0166EJ0600 Rev. 6.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Appendix C I/O Port Block Diagrams R Q D PGnDDR C WDDRG Reset PGn Modes 4 to 6 Internal data bus Reset R Q D PGnDR C WDRG Bus controller Chip select RDRG RPORG Legend: WDDRG: WDRG: RDRG: RPORG: n = 2 or 3 Write to PGDDR Write to PGDR Read PGDR Read port G Figure C.24 (c) Port G Block Diagram (Pins PG2 and PG3) Page 1420 of 1434 R01UH0166EJ0600 Rev. 6.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Appendix C I/O Port Block Diagrams Modes 4/5 Modes 6/7 S R Q D PG4DDR C WDDRG Reset PG4 Modes 4 to 6 Internal data bus Reset R Q D PG4DR C WDRG Bus controller Chip select RDRG RPORG Legend: WDDRG: WDRG: RDRG: RPORG: Write to PGDDR Write to PGDR Read PGDR Read port G Figure C.24 (d) Port G Block Diagram (Pin PG4) R01UH0166EJ0600 Rev. 6.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Appendix D Pin States Appendix D Pin States D.1 Port States in Each Mode Table D.1 lists the I/O port states in each processing mode for the H8S/2633, H8S/2632, H8S/2631, H8S/2633F, and H8S/2633R. Table D.2 lists the I/O port states in each processing mode for the H8S/2695. Table D.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Appendix D Pin States MCU Port Name Operating Pin Name Mode PowerOn Manual Reset Reset Hardware Software Standby Standby Mode Mode Bus Release State Program Execution State Sleep Mode Port C 4, 5 L kept T [OPE = 0] T [OPE = 1] kept T A7 to A0 6 T kept T [DDR = 1, OPE = 0] T [DDR = 1, OPE = 1] kept [DDR = 0] kept T [DDR = 1] A7 to A0 [DDR = 0] I/O port 7 T kept T kept kept I/O port 4 to 6 T T* T T T Data b
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Appendix D Pin States MCU Port Name Operating Pin Name Mode PF5/RD PF4/HWR PF3/LWR/ ADTRG/ IRQ3 Hardware Software Standby Standby Mode Mode Bus Release State 4 to 6 H H T [OPE = 0] T [OPE = 1] H T RD, HWR, LWR 7 T kept T kept kept I/O port T [CAS output] H [Otherwise] kept T [LCAS output, OPE = 0] T [LCAS output, OPE = 1] LCAS [Otherwise] kept [LCAS output] T [BREQOE = 1] BREQO [WAITE = 1] T [LCAS output] LCAS [BREQOE
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Appendix D Pin States Program Execution State Sleep Mode MCU Port Name Operating Pin Name Mode PowerOn Manual Reset Reset Hardware Software Standby Standby Mode Mode Bus Release State PG3/CS1 PG2/CS2 T kept T [DDR = 1, OPE = 0] T [DDR = 1, OPE = 1] H [DDR = 0] T T [DDR = 0] Input port [DDR = 1] CS2 to CS1 7 T kept T kept kept I/O port 4 to 6 T kept T [DDR = 1, OPE = 0] T [DDR = 1, OPE = 1] H [DDR = 0] T T [DDR =
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Appendix D Pin States Table D.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Appendix D Pin States MCU Port Name Operating Pin Name Mode PowerOn Manual Reset Reset Hardware Software Standby Standby Mode Mode Bus Release State Program Execution State Sleep Mode Port C 4, 5 L kept T [OPE = 0] T [OPE = 1] kept T A7 to A0 6 T kept T [DDR = 1, OPE = 0] T [DDR = 1, OPE = 1] kept [DDR = 0] kept T [DDR = 1] A7 to A0 [DDR = 0] I/O port 7 T kept T kept kept I/O port T T* T T T Data bus Port
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Appendix D Pin States MCU Port Name Operating Pin Name Mode PF5/RD PF4/HWR PF3/LWR/ ADTRG/ IRQ3 Hardware Software Standby Standby Mode Mode Bus Release State 4 to 6 H H T [OPE = 0] T [OPE = 1] H T RD, HWR, LWR 7 T kept T kept kept I/O port T kept T kept [BREQOE = 1] BREQO [WAITE = 1] T [BREQOE = 1] BREQO [WAITE = 1] WAIT 7 T kept T kept kept I/O port 4 to 6 T kept T [BRLE = 0] I/O port [BRLE = 1] H [BRLE =
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Appendix D Pin States Program Execution State Sleep Mode MCU Port Name Operating Pin Name Mode PowerOn Manual Reset Reset Hardware Software Standby Standby Mode Mode Bus Release State PG3/CS1 PG2/CS2 4 to 6 T kept T [DDR = 1, OPE = 0] T [DDR = 1, OPE = 1] H [DDR = 0] T T [DDR = 0] Input port [DDR = 1] CS2 to CS1 7 T kept T kept kept I/O port 4 to 6 T kept T [DDR = 1, OPE = 0] T [DDR = 1, OPE = 1] H [DDR = 0] T T
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Appendix E Timing of Transition to and Recovery from Hardware Standby Mode Appendix E Timing of Transition to and Recovery from Hardware Standby Mode Timing of Transition to Hardware Standby Mode (1) To retain RAM contents with the RAME bit set to 1 in SYSCR, drive the RES signal low at least 10 states before the STBY signal goes low, as shown below.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 Appendix F Product Code Lineup Appendix F Product Code Lineup Table F.
H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 Appendix G Package Dimensions Appendix G Package Dimensions The package dimension that is shown in the Renesas Semiconductor Package Data Book has priority. Figures G.1 and G.2 show the TFP-120 and FP-128 package dimensions of the H8S/2633 Group, H8S/2633F, H8S/2633R, and H8S/2695. JEITA Package Code P-TQFP120-14x14-0.40 RENESAS Code PTQP0120LA-A Previous Code TFP-120/TFP-120V MASS[Typ.] 0.5g HD *1 D 90 NOTE) 1.
TM H8S/2633 Group, H8S/2633 F-ZTAT , TM H8S/2633R F-ZTAT , H8S/2695 JEITA Package Code P-QFP128-14x20-0.50 Appendix G Package Dimensions RENESAS Code PRQP0128KB-A Previous Code FP-128B/FP-128BV MASS[Typ.] 1.7g HD *1 NOTE) 1. DIMENSIONS"*1"AND"*2" DO NOT INCLUDE MOLD FLASH 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET. D 102 65 103 64 Reference Symbol HE b1 ZE 1 Terminal cross section ZD 21.8 22.0 HE 15.8 16.0 A2 0.00 0.10 0.25 bp 0.17 0.22 0.27 0.12 0.17 bp x 0.
Appendix G Package Dimensions Page 1434 of 1434 H8S/2633 Group, H8S/2633 F-ZTATTM, TM H8S/2633R F-ZTAT , H8S/2695 R01UH0166EJ0600 Rev. 6.
Renesas 16-Bit Single-Chip Microcomputer H8S/2633 Group, H8S/2633 F-ZTATTM, H8S/2633R F-ZTATTM, H8S/2695 User's Manual: Hardware Publication Date: Rev.1.00, December, 1998 Rev.6.
http://www.renesas.com SALES OFFICES Refer to "http://www.renesas.com/" for the latest and detailed information. Renesas Electronics America Inc. 2880 Scott Boulevard Santa Clara, CA 95050-2554, U.S.A. Tel: +1-408-588-6000, Fax: +1-408-588-6130 Renesas Electronics Canada Limited 1101 Nicholson Road, Newmarket, Ontario L3Y 9C3, Canada Tel: +1-905-898-5441, Fax: +1-905-898-3220 Renesas Electronics Europe Limited Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.
H8S/2633 Group, H8S/2633 F-ZTATTM, H8S/2633R F-ZTATTM, H8S/2695 User's Manual: Hardware R01UH0166EJ0600 (Previous Number: REJ09B0234-0500)
