Datasheet

Section 1 Overview
Page 44 of 1434 R01UH0166EJ0600 Rev. 6.00
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
Type Symbol I/O Name and Function
System control RES Input Reset input: When this pin is driven low, the chip is
reset.
MRES Input Manual reset: When this pin is driven low, a
transmission is made to manual reset mode.
STBY Input Standby: When this pin is driven low, a transition is
made to hardware standby mode.
BREQ Input Bus request: Used by an external bus master to issue
a bus request to the H8S/2633 Group.
BREQO Output Bus request output: The external bus request signal
used when an internal bus master accesses external
space in the external bus-released state.
BACK Output Bus request acknowledge: Indicates that the bus has
been released to an external bus master.
Interrupts NMI Input Nonmaskable interrupt: Requests a nonmaskable
interrupt. When this pin is not used, it should be fixed
high.
IRQ7 to IRQ0 Input Interrupt request 7 to 0: These pins request a
maskable interrupt.
Address bus A23 to A0 Output Address bus: These pins output an address.
Data bus D15 to D0 I/O Data bus: These pins constitute a bidirectional data
bus.
Bus control CS7 to CS0 Output Chip select: Selection signal for areas 0 to 7.
AS Output Address strobe: When this pin is low, it indicates that
address output on the address bus is enabled.
RD Output Read: When this pin is low, it indicates that the
external address space can be read.
HWR Output High write/write enable/upper write enable:
A strobe signal that writes to external space and
indicates that the upper half (D15 to D8) of the data
bus is enabled.
The 2CAS type DRAM write enable signal.
The 2WE type DRAM upper write enable signal.