Datasheet

Section 1 Overview
R01UH0166EJ0600 Rev. 6.00 Page 45 of 1434
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
Type Symbol I/O Name and Function
Bus control LWR Output Low write/lower column address strobe/lower write
enable:
A strobe signal that writes to external space and
indicates that the lower half (D7 to D0) of the data bus
is enabled.
The 2CAS type (LCASS = 1) DRAM lower column
address strobe signal.
The 2WE type DRAM lower write enable signal.
WAIT Input Wait: Requests insertion of a wait state in the bus
cycle when accessing external 3-state address space.
16-bit timer-
pulse unit (TPU)
TCLKD to
TCLKA
Input Clock input D to A: These pins input an external clock.
TIOCA0,
TIOCB0,
TIOCC0,
TIOCD0
I/O Input capture/ output compare match A0 to D0:
The TGR0A to TGR0D input capture input or output
compare output, or PWM output pins.
TIOCA1,
TIOCB1
I/O Input capture/ output compare match A1 and B1:
The TGR1A and TGR1B input capture input or output
compare output, or PWM output pins.
TIOCA2,
TIOCB2
I/O Input capture/ output compare match A2 and B2:
The TGR2A and TGR2B input capture input or output
compare output, or PWM output pins.
TIOCA3,
TIOCB3,
TIOCC3,
TIOCD3
I/O Input capture/ output compare match A3 to D3:
The TGR3A to TGR3D input capture input or output
compare output, or PWM output pins.
TIOCA4,
TIOCB4
I/O Input capture/output compare match A4 and B4:
The TGR4A and TGR4B input capture input or output
compare output, or PWM output pins.
TIOCA5,
TIOCB5
I/O Input capture/output compare match A5 and B5:
The TGR5A and TGR5B input capture input or output
compare output, or PWM output pins.
Watchdog
timer (WDT)
WDTOVF Output Watchdog timer overflows: The counter overflows
signal output pin in watchdog timer mode.