Datasheet

Section 22 ROM
R01UH0166EJ0600 Rev. 6.00 Page 957 of 1434
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
22.5.4 Erase Block Register 2 (EBR2)
Bit: 7 6 5 4 3 2 1 0
— — — — EB11 EB10 EB9 EB8
Initial value: 0 0 0 0 0 0 0 0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
EBR2 is an 8-bit register that specifies the flash memory erase area block by block. EBR2 is
initialized to H'00 by a power-on reset, in hardware standby mode and software standby mode,
when a low level is input to the FWE pin. Bit 0 will be initialized to 0 if bit SWE1 of FLMCR1 is
not set, even though a high level is input to pin FWE. When a bit in EBR2 is set to 1, the
corresponding block can be erased. Other blocks are erase-protected. Only one of the bits of EBR1
and EBR2 combined can be set. Do not set more than one bit, as this will cause all the bits in both
EBR1 and EBR2 to be automatically cleared to 0. Bits 7 to 4 are reserved and must only be
written with 0. When on-chip flash memory is disabled, a read will return H'00, and writes are
invalid.
The flash memory erase block configuration is shown in table 22.7.
Table 22.7 Flash Memory Erase Blocks
Block (Size) Addresses
EB0 (4 kbytes) H'000000 to H'000FFF
EB1 (4 kbytes) H'001000 to H'001FFF
EB2 (4 kbytes) H'002000 to H'002FFF
EB3 (4 kbytes) H'003000 to H'003FFF
EB4 (4 kbytes) H'004000 to H'004FFF
EB5 (4 kbytes) H'005000 to H'005FFF
EB6 (4 kbytes) H'006000 to H'006FFF
EB7 (4 kbytes) H'007000 to H'007FFF
EB8 (32 kbytes) H'008000 to H'00FFFF
EB9 (64 kbytes) H'010000 to H'01FFFF
EB10 (64 kbytes) H'020000 to H'02FFFF
EB11 (64 kbytes) H'030000 to H'03FFFF