Datasheet

Section 22 ROM
Page 960 of 1434 R01UH0166EJ0600 Rev. 6.00
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
22.5.6 Flash Memory Power Control Register (FLPWCR)
Bit: 7 6 5 4 3 2 1 0
PDWND — — — — — — —
Initial value: 0 0 0 0 0 0 0 0
R/W: R/W R R R R R R R
FLPWCR enables or disables a transition to the flash memory power-down mode when the LSI
switches to subactive mode.
Bit 7—Power-Down Disable (PDWND): Enables or disables a transition to the flash memory
power-down mode when the LSI switches to subactive mode.
Bit 7
PDWND Description
0 Transition to flash memory power-down mode enabled (Initial value)
1 Transition to flash memory power-down mode disabled
Bits 6 to 0—Reserved: These bits always read 0.
22.5.7 Serial Control Register X (SCRX)
Bit: 7 6 5 4 3 2 1 0
— IICX1 IICX0 IICE FLSHE — — —
Initial value: 0 0 0 0 0 0 0 0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
SCRX is an 8-bit readable/writable register that controls on-chip flash memory.
SCRX is initialized to H'00 by a reset and in hardware standby mode.
Bit 7—Reserved: This bit should always be written with 0.
Bits 6 and 5—I
2
C Transfer Rate Select (IICX1 and IICX0): These bits, together with bits
CKS2 to CKS0 in ICMR, select the transfer rate in master mode. For details of the transfer rate,
see section 18.2.4, I
2
C Bus Mode Register (ICMR).