Datasheet

Section 22 ROM
R01UH0166EJ0600 Rev. 6.00 Page 979 of 1434
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
Figure 22.15 shows the flash memory state transition diagram.
RD VF PR ER FLER = 0
Error
occurrence
RES = 0 or HSTBY = 0
RES = 0 or
HSTBY = 0
RD VF PR ER FLER = 0
Program mode
Erase mode
Reset or standby
(hardware protection)
RD VF PR ER FLER = 1
RD VF PR ER FLER = 1
Error protection mode
Error protection mode
(software standby)
Software
standby mode
FLMCR1, FLMCR2, (except bit FLER)
EBR1, EBR2 initialization state
FLMCR1, FLMCR2,
EBR1, EBR2
initialization state
Software standby
mode release
RD: Memory read possible
VF: Verify-read possible
PR: Programming possible
ER: Erasing possible
RD: Memory read not possible
VF: Verify-read not possible
PR: Programming not possible
ER: Erasing not possible
Legend:
RES = 0 or
HSTBY = 0
Error occurrence
(software standby)
Figure 22.15 Flash Memory State Transitions