Datasheet

Section 22 ROM
Page 988 of 1434 R01UH0166EJ0600 Rev. 6.00
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
Period during which flash memory access is prohibited
(x: Wait time after setting SWE1 bit)
*2
Period during which flash memory can be programmed
(Execution of program in flash memory prohibited, and data reads other than verify operations
prohibited)
φ
V
CC
FWE
t
OSC1
Min 0 μs
Min 0 μs
t
MDS
*3
t
MDS
*3
MD2 to MD0
*1
RES
SWE1 bit
SWE1 set
SWE1 cleared
Programming/
erasing
possible
Wait time: x Wait time: 100 μs
Notes: 1. Except when switching modes, the level of the mode pins (MD2 to MD0) must be fixed until
power-off by pulling the pins up or down.
2. See section 25.6 and 26.6, Flash Memory Characteristics.
3. Mode programming setup time t
MDS
(min) = 200 ns
Figure 22.19 Power-On/Off Timing (Boot Mode)