Datasheet

Section 23A Clock Pulse Generator
(H8S/2633, H8S/2632, H8S/2631, H8S/2633F)
R01UH0166EJ0600 Rev. 6.00 Page 993 of 1434
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
Section 23A Clock Pulse Generator
(H8S/2633, H8S/2632, H8S/2631, H8S/2633F)
23A.1 Overview
The H8S/2633 Group has a built-in clock pulse generator (CPG) that generates the system clock
(φ), the bus master clock, and internal clocks.
The clock pulse generator consists of an oscillator, PLL (phase-locked loop) circuit, clock
selection circuit, medium-speed clock divider, bus master clock selection circuit, subclock
oscillator, and waveform shaping circuit. The frequency can be changed by means of the PLL
circuit in the CPG. Frequency changes are performed by software by means of settings in the
system clock control register (SCKCR) and low-power control register (LPWRCR).
23A.1.1 Block Diagram
Figure 23A.1 shows a block diagram of the clock pulse generator.
Legend:
LPWRCR:
SCKCR:
Low-power control register
System clock control register
EXTAL
XTAL
PLL circuit
(×1, ×2, ×4)
Medium-
speed
clock divider
System
clock
oscillator
Clock
selection
circuit
φSUB
WDT1 count clock
System clock
to φ pin
Internal clock to
supporting modules
Bus master cloc
k
to CPU, DMAC
and DTC
φ/2 to
φ/32
φ
SCK2 to SCK0
SCKCR
STC1, STC0
OSC1
OSC2
Waveform
shaping
circuit
Subclock
oscillator
LPWRCR
Bus
master
clock
selection
circuit
Figure 23A.1 Block Diagram of Clock Pulse Generator