Datasheet

Section 23A Clock Pulse Generator
(H8S/2633, H8S/2632, H8S/2631, H8S/2633F)
Page 994 of 1434 R01UH0166EJ0600 Rev. 6.00
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
23A.1.2 Register Configuration
The clock pulse generator is controlled by SCKCR and LPWRCR. Table 23A.1 shows the register
configuration.
Table 23A.1 Clock Pulse Generator Register
Name Abbreviation R/W Initial Value Address
*
System clock control register SCKCR R/W H'00 H'FDE6
Low-power control register LPWRCR R/W H'00 H'FDEC
Note: * Lower 16 bits of the address.
23A.2 Register Descriptions
23A.2.1 System Clock Control Register (SCKCR)
7
PSTOP
0
R/W
6
—
0
—
5
—
0
—
4
—
0
—
3
STCS
0
R/W
0
SCK0
0
R/W
2
SCK2
0
R/W
1
SCK1
0
R/W
Bit
Initial value
R/W
:
:
:
SCKCR is an 8-bit readable/writable register that performs φ clock output control, selection of
operation when the PLL circuit frequency multiplication factor is changed, and medium-speed
mode control.
SCKCR is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bit 7—φ Clock Output Disable (PSTOP): Controls φ output.
Description
Bit 7
PSTOP
High-Speed Mode,
Medium-Speed Mode,
Subactive Mode
Sleep Mode
Subsleep Mode
Software
Standby Mode,
Watch Mode,
Direct Transitions
Hardware
Standby Mode
0 φ output (initial value) φ output Fixed high High impedance
1 Fixed high Fixed high Fixed high High impedance