Datasheet

Section 23A Clock Pulse Generator
(H8S/2633, H8S/2632, H8S/2631, H8S/2633F)
Page 996 of 1434 R01UH0166EJ0600 Rev. 6.00
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
Bits 1 and 0—Frequency Multiplication Factor (STC1, STC0): The STC bits specify the
frequency multiplication factor of the PLL circuit.
Bit 1 Bit 0
STC1 STC0 Description
0 0 ×1 (Initial value)
1 ×2
1 0 ×4
1 Setting prohibited
Note: A system clock frequency multiplied by the multiplication factor (STC1 and STC0) should
not exceed the maximum operating frequency defined in section 25, Electrical
Characteristics.
Current consumption and noise can be reduced by using this function’s PLL ×4 setting and
lowering the external clock frequency.
23A.3 Oscillator
Clock pulses can be supplied by connecting a crystal resonator, or by input of an external clock.
23A.3.1 Connecting a Crystal Resonator
Circuit Configuration: A crystal resonator can be connected as shown in the example in figure
23A.2. Select the damping resistance R
d
according to table 23A.2. An AT-cut parallel-resonance
crystal should be used.
EXTAL
XTAL
R
d
C
L2
C
L1
C
L1
= C
L2
= 10 to 22pF
Figure 23A.2 Connection of Crystal Resonator (Example)