Datasheet

Section 2 CPU

Page 50 of 1434 R01UH0166EJ0600 Rev. 6.00

Mar 02, 2011

H8S/2633 Group, H8S/2633 F-ZTAT

H8S/2633R F-ZTAT

, H8S/2695

• High-speed operation

⎯ All frequently-used instructions execute in one or two states

⎯ Maximum clock rate: 25 MHz (H8S/2633, H8S/2633F, H8S/2632, H8S/2631),

28 MHz (H8S/2633R, H8S/2695)

⎯ 8/16/32-bit register-register add/subtract: 40 ns (25 MHz), 35 ns (28 MHz)

⎯ 8 • 8-bit register-register multiply: 120 ns (25 MHz), 105 ns (28 MHz)

⎯ 16 ÷ 8-bit register-register divide: 480 ns (25 MHz), 420 ns (28 MHz)

⎯ 16 • 16-bit register-register multiply: 160 ns (25 MHz), 140 ns (28 MHz)

⎯ 32 ÷ 16-bit register-register divide: 800 ns (25 MHz), 700 ns (28 MHz)

• Two CPU operating modes

⎯ Normal mode*

⎯ Advanced mode

Note: * Not available in the H8S/2633 Group.

• Power-down state

⎯ Transition to power-down state by SLEEP instruction

⎯ CPU clock speed selection

2.1.2 Differences between H8S/2600 CPU and H8S/2000 CPU

The differences between the H8S/2600 CPU and the H8S/2000 CPU are as shown below.

• Register configuration

The MAC register is supported only by the H8S/2600 CPU.

• Basic instructions

The four instructions MAC, CLRMAC, LDMAC, and STMAC are supported only by the

H8S/2600 CPU.

• Number of execution states

The number of execution states of the MULXU and MULXS instructions is different in each

CPU.