Datasheet

Section 23B Clock Pulse Generator
(H8S/2633R, H8S/2695)
Page 1006 of 1434 R01UH0166EJ0600 Rev. 6.00
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
23B.1.1 Block Diagram
Figure 23B.1 shows a block diagram of the clock pulse generator.
Legend:
LPWRCR:
SCKCR:
Notes: 1. This function is not available in the H8S/2695.
2. The input clock frequency is 2 MHz to 25 MHz. With the H8S/2633R and H8S/2695 PLL must be set to use
a multiplier of × 2 or × 4 when operating at frequencies of 25 MHz < φ ≤ 28 MHz.
Low-power control register
System clock control register
EXTAL
XTAL
PLL circuit
(×1, ×2, ×4)
Medium-
speed
clock divider
System
clock
oscillator
Clock
selection
circuit
φSUB
WDT1
count
clock
System clock
to φ pin
Internal clock to
supporting modules
Bus master cloc
k
to CPU, DMAC
*1
and DTC
*1
φ/2 to
φ/32
φ
SCK2 to SCK0
SCKCR
STC1, STC0
OSC1
OSC2
Waveform
shaping
circuit
Subclock
oscillator
LPWRCR
Bus
master
clock
selection
circuit
*
1
*2
Figure 23B.1 Block Diagram of Clock Pulse Generator
23B.1.2 Register Configuration
The clock pulse generator is controlled by SCKCR and LPWRCR. Table 23B.1 shows the register
configuration.
Table 23B.1 Clock Pulse Generator Register
Name Abbreviation R/W Initial Value Address
*
System clock control register SCKCR R/W H'00 H'FDE6
Low-power control register LPWRCR R/W H'00 H'FDEC
Note: * Lower 16 bits of the address.