Datasheet

Section 23B Clock Pulse Generator
(H8S/2633R, H8S/2695)
Page 1008 of 1434 R01UH0166EJ0600 Rev. 6.00
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
Bits 2 to 0—System Clock Select 2 to 0 (SCK2 to SCK0): These bits select the bus master
clock.
Bit 2 Bit 1 Bit 0
SCK2 SCK1 SCK0 Description
0 0 0 Bus master is in high-speed mode (Initial value)
1 Medium-speed clock is φ/2
1 0 Medium-speed clock is φ/4
1 Medium-speed clock is φ/8
1 0 0 Medium-speed clock is φ/16
1 Medium-speed clock is φ/32
1 — —
23B.2.2 Low-Power Control Register (LPWRCR)
7
DTON
0
R/W
6
LSON
0
R/W
5
NESEL
0
R/W
4
SUBSTP
0
R/W
3
RFCUT
0
R/W
0
STC0
0
R/W
2
—
0
R/W
1
STC1
0
R/W
Bit :
Initial value :
R/W :
Note: * In the H8S/2695 only 0 should be written to these bits.
H8S/2633R
7
—*
0
R
6
—*
0
R
5
—*
0
R/W
4
—*
0
R/W
3
—*
0
R/W
0
STC0
0
R/W
2
—
0
R/W
1
STC1
0
R/W
Bit :
Initial value :
R/W :
H8S/2695
LPWRCR is an 8-bit readable/writable register that performs power-down mode control. The
following pertains to bits 1 and 0. For details of the other bits, see section 24.2.3, Low-Power
Control Register (LPWRCR). LPWRCR is initialized to H'00 by a reset and in hardware standby
mode. It is not initialized in software standby mode.