Datasheet

Section 23B Clock Pulse Generator
(H8S/2633R, H8S/2695)
R01UH0166EJ0600 Rev. 6.00 Page 1009 of 1434
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
Bits 1 and 0—Frequency Multiplication Factor (STC1, STC0): The STC bits specify the
frequency multiplication factor of the PLL circuit.
Bit 1 Bit 0
STC1 STC0 Description
0 0 ×1 (Initial value)
1 ×2
1 0 ×4
1 Setting prohibited
Note: A system clock frequency multiplied by the multiplication factor (STC1 and STC0) should
not exceed the maximum operating frequency defined in sections 26 and 27, Electrical
Characteristics.
Current consumption and noise can be reduced by using this function’s PLL ×4 setting and
lowering the external clock frequency.
The input clock frequency is 2 MHz to 25 MHz. With the H8S/2633R and H8S/2695 PLL
must be set to use a multiplier of × 2 or × 4 when operating at frequencies of 25 MHz < φ
≤ 28 MHz.
23B.3 Oscillator
Clock pulses can be supplied by connecting a crystal resonator, or by input of an external clock.
23B.3.1 Connecting a Crystal Resonator
Circuit Configuration: A crystal resonator can be connected as shown in the example in figure
23B.2. Select the damping resistance R
d
according to table 23B.2. An AT-cut parallel-resonance
crystal should be used.
EXTAL
XTAL
R
d
C
L2
C
L1
C
L1
= C
L2
= 10 pF to 22 pF
if 2 MHz ≤ φ < 20 MHz
C
L1
= C
L2
= 10 pF
if 20 MHz ≤ φ ≤ 25 MHz
Figure 23B.2 Connection of Crystal Resonator (Example)