Datasheet

Section 24 Power-Down Modes

R01UH0166EJ0600 Rev. 6.00 Page 1017 of 1434

Mar 02, 2011

H8S/2633 Group, H8S/2633 F-ZTAT

H8S/2633R F-ZTAT

, H8S/2695

Section 24 Power-Down Modes

24.1 Overview

In addition to the normal program execution state, the H8S/2633 Group has eight power-down

modes in which operation of the CPU and oscillator is halted and power dissipation is reduced.

Low-power operation can be achieved by individually controlling the CPU, on-chip supporting

modules, and so on.

The H8S/2633 Group operating modes are as follows:

(1) High-speed mode

(2) Medium-speed mode

(3) Subactive mode

(4) Sleep mode

(5) Subsleep mode

(6) Watch mode

(7) Module stop mode

(8) Software standby mode

(9) Hardware standby mode

(2) to (9) are power down modes. Sleep mode and subsleep mode are CPU mode, medium-speed

mode is a CPU and bus master mode, subactive mode is a CPU and bus master and on-chip

supporting module mode, and module stop mode is an on-chip supporting module mode

(including bus masters other than the CPU) state. Some of these modes can be combined.

After a reset, the LSI is in high-speed mode, with modules other than the DMAC and DTC in

module stop mode.

Table 24.1 shows the internal states of the LSI in the respective modes. Table 24.2 shows the

conditions for shifting between the power-down modes.

Figure 24.1 is a mode transition diagram.

Note: * This function is not available in the H8S/2695.