Datasheet

Section 24 Power-Down Modes
R01UH0166EJ0600 Rev. 6.00 Page 1023 of 1434
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
24.2 Register Descriptions
24.2.1 Standby Control Register (SBYCR)
7
SSBY
0
R/W
6
STS2
0
R/W
5
STS1
0
R/W
4
STS0
0
R/W
3
OPE
1
R/W
0
—
0
—
2
—
0
—
1
—
0
—
Bit
Initial value
R/W
:
:
:
SBYCR is an 8-bit readable/writable register that performs power-down mode control.
SBYCR is initialized to H'08 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bit 7—Software Standby (SSBY): When making a low power dissipation mode transition by
executing the SLEEP instruction, the operating mode is determined in combination with other
control bits.
Note that the value of the SSBY bit does not change even when shifting between modes using
interrupts.
Bit 7
SSBY Description
0 Shifts to sleep mode when the SLEEP instruction is executed in high-speed
mode or medium-speed mode.
Shifts to subsleep mode
*
when the SLEEP instruction is executed in
subactive mode
*
. (Initial value)
1 Shifts to software standby mode, subactive mode
*
, and watch mode
*
when the
SLEEP instruction is executed in high-speed mode or medium-speed mode.
Shifts to watch mode
*
or high-speed mode when the SLEEP instruction is executed in
subactive mode
*
.
Note: * This function is not available in the H8S/2695.