Datasheet

Section 24 Power-Down Modes
Page 1024 of 1434 R01UH0166EJ0600 Rev. 6.00
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
Bits 6 to 4—Standby Timer Select 2 to 0 (STS2 to STS0): These bits select the MCU wait time
for clock stabilization when shifting to high-speed mode or medium-speed mode by using a
specific interrupt or command to cancel software standby mode, watch mode
*
, or subactive
mode
*
. With a crystal oscillator (table 24.5), select a wait time of 8 ms (oscillation stabilization
time) or more, depending on the operating frequency. With an external clock, select a wait time of
2 ms (PLL oscillator stabilization time) or more, depending on the operating frequency.
Note: * This function is not available in the H8S/2695.
Bit 6 Bit 5 Bit 4
STS2 STS1 STS0 Description
0 0 0 Standby time = 8192 states (Initial value)
1 Standby time = 16384 states
1 0 Standby time = 32768 states
1 Standby time = 65536 states
1 0 0 Standby time = 131072 states
1 Standby time = 262144 states
1 0 Reserved
1 Standby time = 16 states (Setting prohibited)
Bit 3—Output Port Enable (OPE): This bit specifies whether the output of the address bus and
bus control signals (CS0 to CS7, AS, RD, HWR, LWR, CAS, and OE) is retained or set to high-
impedance state in the software standby mode, watch mode, and when making a direct transition.
Bit 3
OPE Description
0 In software standby mode, watch mode
*
, and when making a direct transition
*
,
address bus and bus control signals are high-impedance.
1 In software standby mode, watch mode
*
, and when making a direct transition
*
, the
output state of the address bus and bus control signals is retained. (Initial value)
Note: * This function is not available in the H8S/2695.
Bits 2 to 0—Reserved: These bits are always read as 0 and cannot be modified.