Datasheet

Section 24 Power-Down Modes
R01UH0166EJ0600 Rev. 6.00 Page 1025 of 1434
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
24.2.2 System Clock Control Register (SCKCR)
7
PSTOP
0
R/W
6
—
0
—
5
—
0
—
4
—
0
—
3
STCS
0
R/W
0
SCK0
0
R/W
2
SCK2
0
R/W
1
SCK1
0
R/W
Bit
Initial value
R/W
:
:
:
SCKCR is an 8-bit readable/writable register that performs φ clock output control, selection of
operation when the PLL circuit frequency multiplication factor is changed, and medium-speed
mode control.
SCKCR is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bit 7—φ Clock Output Disable (PSTOP): In combination with the DDR of the applicable port,
this bit controls φ output. See section 24.12, φ Clock Output Disabling Function, for details.
Description
Bit 7
PSTOP
High-Speed Mode,
Medium-Speed Mode,
Subactive Mode
*
Sleep Mode,
Subsleep Mode
*
Software Standby
Mode, Watch Mode
*
,
Direct Transition
Hardware Standby
Mode
0 φ output (initial value) φ output Fixed high High impedance
1 Fixed high Fixed high Fixed high High impedance
Note: * This function is not available in the H8S/2695.
Bits 6 to 4—Reserved: These bits are always read as 0 and cannot be modified.
Bit 3—Frequency Multiplication Factor Switching Mode Select (STCS): Selects the operation
when the PLL circuit frequency multiplication factor is changed.
Bit 3
STCS Description
0 Specified multiplication factor is valid after transition to software standby mode, watch
mode
*
, or subactive mode
*
(Initial value)
1 Specified multiplication factor is valid immediately after STC bits are rewritten
Note: * This function is not available in the H8S/2695.