Datasheet

Section 24 Power-Down Modes
Page 1026 of 1434 R01UH0166EJ0600 Rev. 6.00
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
Bits 2 to 0—System Clock Select (SCK2 to SCK0): These bits select the bus master clock in
high-speed mode, medium-speed mode, and subactive mode
*
.
Set SCK2 to SCK0 all to 0 when shifting to operation in watch mode or subactive mode
*
.
Note: * This function is not available in the H8S/2695.
Bit 2 Bit 1 Bit 0
SCK2 SCK1 SCK0 Description
0 0 0 Bus master in high-speed mode (Initial value)
1 Medium-speed clock is φ/2
1 0 Medium-speed clock is φ/4
1 Medium-speed clock is φ/8
1 0 0 Medium-speed clock is φ/16
1 Medium-speed clock is φ/32
1 — —
24.2.3 Low-Power Control Register (LPWRCR)
7
DTON
0
R/W
6
LSON
0
R/W
5
NESEL
0
R/W
4
SUBSTP
0
R/W
3
RFCUT
0
R/W
0
STC0
0
R/W
2
—
0
R/W
1
STC1
0
R/W
Bit
Initial value
R/W
H8S/2633 Group, H8S/2633R
:
:
:
7
—
*
0
R
6
—
*
0
R
5
—
*
0
R/W
4
—
*
0
R/W
3
—
*
0
R/W
0
STC0
0
R/W
2
—
0
R/W
1
STC1
0
R/W
Bit
Initial value
R/W
Note: * On the H8S/2695 only 0 should be written to these bits.
H8S/2695
:
:
:
The LPWRCR is an 8-bit read/write register that controls the low power dissipation modes.
The LPWRCR is initialized to H'00 at a power-on reset and when in hardware standby mode. It is
not initialized at a manual reset or when in software standby mode. The following describes bits 7