Datasheet

Section 24 Power-Down Modes
R01UH0166EJ0600 Rev. 6.00 Page 1029 of 1434
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
Bit 3—Oscillation Circuit Feedback Resistance Control Bit (RFCUT): This bit turns the
internal feedback resistance of the main clock oscillation circuit ON/OFF.
Bit 3
RFCUT Description
0 When the main clock is oscillating, sets the feedback resistance ON. When the main
clock is stopped, sets the feedback resistance OFF (Initial value)
1 Sets the feedback resistance OFF
Bit 2—Reserved: Should always be written with 0.
24.2.4 Timer Control/Status Register (TCSR)
WDT1 TCSR
7
OVF
0
R/(W)*
6
WT/IT
0
R/W
5
TME
0
R/W
4
PSS
0
R/W
3
RST/NMI
0
R/W
0
CKS0
0
R/W
2
CKS2
0
R/W
1
CKS1
0
R/W
Bit
Initial value
R/W
:
:
:
Note: * Only write 0 to clear the flag.
TCSR is an 8-bit read/write register that selects the clock input to WDT1 TCNT and the mode.
The following describes bit 4. For details of the other bits in this register, see section 15.2.2, Timer
Control/Status Register (TCSR).
The TCSR is initialized to H'00 at a reset and when in hardware standby mode. It is not initialized
in software standby mode.
Bit 4—Prescaler select (PSS)
*
1
: This bit selects the clock source input to WDT1 TCNT.
It also controls operation when shifting low power dissipation modes. The operating mode
selected after the SLEEP instruction is executed is determined in combination with other control
bits.
For details, see the description for clock selection in section 15.2.2, Timer Control/Status Register
(TCSR), and this section.