Datasheet

Section 24 Power-Down Modes
Page 1030 of 1434 R01UH0166EJ0600 Rev. 6.00
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
WDT1
TCSR
Bit 4
PSS
*
1
Description
0
• TCNT counts the divided clock from the φ-based prescaler (PSM).
• When the SLEEP instruction is executed in high-speed mode or medium-speed
mode, operation shifts to sleep mode or software standby mode. (Initial value)
1
• TCNT counts the divided clock from the φsubclock-based prescaler (PSS).
• When the SLEEP instruction is executed in high-speed mode or medium-speed
mode, operation shifts to sleep mode, watch mode
*
2
, or subactive mode
*
2
.
• When the SLEEP instruction is executed in subactive mode, operation shifts to
subsleep mode, watch mode, or high-speed mode.
Notes: 1. In the H8S/2695 only a 0 may be written to the PSS bit in the TCSR1 register.
2. Always set high-speed mode when shifting to watch mode or subactive mode.
24.2.5 Module Stop Control Register (MSTPCR)
MSTPCRA
Bit : 7 6 5 4 3 2 1 0
MSTPA7 MSTPA6 MSTPA5 MSTPA4 MSTPA3 MSTPA2 MSTPA1 MSTPA0
Initial value : 0 0 1 1 1 1 1 1
R/W : R/W R/W R/W R/W R/W R/W R/W R/W
MSTPCRB
Bit : 7 6 5 4 3 2 1 0
MSTPB7 MSTPB6 MSTPB5 MSTPB4 MSTPB3 MSTPB2 MSTPB1 MSTPB0
Initial value : 1 1 1 1 1 1 1 1
R/W : R/W R/W R/W R/W R/W R/W R/W R/W
MSTPCRC
Bit : 7 6 5 4 3 2 1 0
MSTPC7 MSTPC6 MSTPC5 MSTPC4 MSTPC3 MSTPC2 MSTPC1 MSTPC0
Initial value : 1 1 1 1 1 1 1 1
R/W : R/W R/W R/W R/W R/W R/W R/W R/W
MSTPCR, comprising three 8-bit readable/writable registers, performs module stop mode control.