Datasheet

Section 24 Power-Down Modes
R01UH0166EJ0600 Rev. 6.00 Page 1033 of 1434
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
(2) Exiting Sleep Mode by RES or MRES Pins
Setting the RES or MRES pin level Low selects the reset state. After the stipulated reset input
duration, driving the RES and MRES pins High starts the CPU performing reset exception
processing.
(3) Exiting Sleep Mode by STBY Pin
When the STBY pin level is driven low, a transition is made to hardware standby mode.
24.5 Module Stop Mode
24.5.1 Module Stop Mode
Module stop mode can be set for individual on-chip supporting modules.
When the corresponding MSTP bit in MSTPCR is set to 1, module operation stops at the end of
the bus cycle and a transition is made to module stop mode. The CPU continues operating
independently.
Table 24.4 shows MSTP bits and the corresponding on-chip supporting modules.
When the corresponding MSTP bit is cleared to 0, module stop mode is cleared and the module
starts operating at the end of the bus cycle. In module stop mode, the internal states of modules
other than the SCI, A/D converter and 14-bit PWM
*
are retained.
After reset clearance, all modules other than DMAC
*
and DTC
*
are in module stop mode.
When an on-chip supporting module is in module stop mode, read/write access to its registers is
disabled.
Note: * This function is not available in the H8S/2695.