Datasheet

Section 24 Power-Down Modes
Page 1040 of 1434 R01UH0166EJ0600 Rev. 6.00
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
Oscillator
Oscillation
stabilization
time
Reset
exception
handling
RES
STBY
Figure 24.4 Hardware Standby Mode Timing
24.8 Watch Mode (This function is not available in the H8S/2695)
24.8.1 Watch Mode
CPU operation makes a transition to watch mode when the SLEEP instruction is executed in high-
speed mode or subactive mode with SBYCR SSBY=1, LPWRCR DTON = 0, and TCSR (WDT1)
PSS = 1.
In watch mode, the CPU is stopped and supporting modules other than WDT1 are also stopped.
The contents of the CPU’s internal registers, the data in internal RAM, and the statuses of the
internal supporting modules (excluding the SCI, ADC, and 14-bit PWM) and I/O ports are
retained.