Datasheet

Section 24 Power-Down Modes

Page 1042 of 1434 R01UH0166EJ0600 Rev. 6.00

Mar 02, 2011

H8S/2633 Group, H8S/2633 F-ZTAT

H8S/2633R F-ZTAT

, H8S/2695

24.9 Subsleep Mode (This function is not available in the H8S/2695)

24.9.1 Subsleep Mode

When the SLEEP instruction is executed with the SBYCR SSBY bit = 0, LPWRCR LSON bit = 1,

and TCSR (WDT1) PSS bit = 1, CPU operation shifts to subsleep mode.

In subsleep mode, the CPU is stopped. Supporting modules other than TMR0 to TMR3, WDT0,

and WDT1 are also stopped. The contents of the CPU’s internal registers, the data in internal

RAM, and the statuses of the internal supporting modules (excluding the SCI, ADC, and 14-bit

PWM) and I/O ports are retained.

24.9.2 Exiting Subsleep Mode

Subsleep mode is exited by an interrupt (interrupts from internal supporting modules, NMI pin, or

IRQ0 to IRQ7), or signals at the RES, MRES, or STBY pins.

(1) Exiting Subsleep Mode by Interrupts

When an interrupt occurs, subsleep mode is exited and interrupt exception processing starts.

In the case of IRQ0 to IRQ7 interrupts, subsleep mode is not cancelled if the corresponding

enable bit has been cleared to 0, and, in the case of interrupts from the internal supporting

modules, the interrupt enable register has been set to disable the reception of that interrupt, or is

masked by the CPU.

(2) Exiting Subsleep Mode by RES or MRES Pins

For exiting subsleep mode by the RES or MRES pins, see (2), Exiting Software Standby Mode by

RES or MRES pins in section 24.6.2, Exiting Software Standby Mode.

(3) Exiting Subsleep Mode by STBY Pin

When the STBY pin level is driven low, a transition is made to hardware standby mode.