Datasheet

Section 24 Power-Down Modes
R01UH0166EJ0600 Rev. 6.00 Page 1045 of 1434
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
24.12 φ Clock Output Disabling Function
Output of the φ clock can be controlled by means of the PSTOP bit in SCKCR, and DDR for the
corresponding port. When the PSTOP bit is set to 1, the φ clock stops at the end of the bus cycle,
and φ output goes high. φ clock output is enabled when the PSTOP bit is cleared to 0. When DDR
for the corresponding port is cleared to 0, φ clock output is disabled and input port mode is set.
Table 24.6 shows the state of the φ pin in each processing state.
Using the on-chip PLL circuit to lower the oscillator frequency or prohibiting external φ clock
output also have the effect of reducing unwanted electromagnetic interference*. Therefore,
consideration should be given to these options when deciding on system board settings.
Note: * Electromagnetic interference: EMI (Electro Magnetic Interference)
Table 24.6 φ Pin State in Each Processing State
DDR 0 1 1
PSTOP — 0 1
Hardware standby mode High impedance High impedance High impedance
Software standby mode, watch
mode
*
, and direct transition
*
High impedance Fixed high Fixed high
Sleep mode and subsleep mode
*
High impedance φ output Fixed high
High-speed mode, medium-speed
mode, and subactive mode
*
High impedance φ output Fixed high
Note: * This function is not available in the H8S/2695.