Datasheet

Section 25 Electrical Characteristics
(H8S/2633, H8S/2632, H8S/2631, H8S/2633F)
R01UH0166EJ0600 Rev. 6.00 Page 1075 of 1434
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
25.3.5 Timing of On-Chip Supporting Modules
Table 25.9 lists the timing of on-chip supporting modules.
Table 25.9 Timing of On-Chip Supporting Modules
Condition A: V
CC
= PLLV
CC
= 3.0 V to 3.6 V, PV
CC
= 3.0 V to 5.5 V, AV
CC
= 3.6 V to 5.5 V
*
1
,
V
ref
= 3.6 V to AV
CC
*
2
, V
SS
= AV
SS
= PLLV
SS
= 0 V, φ = 32.768 kHz
*
3
,
2 to 16 MHz, T
a
= –20°C to +75°C (regular specifications), T
a
= –40°C to +85°C
(wide-range specifications)
Condition B: V
CC
= PLLV
CC
= 3.0 V to 3.6 V, PV
CC
= 4.5 V to 5.5 V, AV
CC
= 4.5 V to 5.5 V,
V
ref
= 4.5 V to AV
CC
, V
SS
= AV
SS
= PLLV
SS
= 0 V, φ = 32.768 kHz
*
3
,
2 to 25 MHz, T
a
= –20°C to +75°C (regular specifications), T
a
= –40°C to +85°C
(wide-range specifications)
Condition A Condition B
Item Symbol Min Max Min Max Unit Test Conditions
I/O port Output data delay
time
t
PWD
— 60 — 40 ns Figure 25.20
Input data setup
time
t
PRS
40 — 25 —
Input data hold
time
t
PRH
40 — 25 —
PPG Pulse output delay
time
t
POD
— 60 — 40 ns Figure 25.21
TPU Timer output
delay time
t
TOCD
— 60 — 40 ns Figure 25.22
Timer input setup
time
t
TICS
40 — 25 —
Timer clock input
setup time
t
TCKS
40 — 25 — ns Figure 25.23
Single
edge
t
TCKWH
1.5 — 1.5 — t
cyc
Timer
clock
pulse
width
Both
edges
t
TCKWL
2.5 — 2.5 —