Datasheet

Section 25 Electrical Characteristics
(H8S/2633, H8S/2632, H8S/2631, H8S/2633F)
Page 1076 of 1434 R01UH0166EJ0600 Rev. 6.00
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
Condition A Condition B
Item Symbol Min Max Min Max Unit Test Conditions
TMR Timer output delay
time
t
TMOD
— 60 — 40 ns Figure 25.24
Timer reset input
setup time
t
TMRS
40 — 25 — ns Figure 25.26
Timer clock input
setup time
t
TMCS
40 — 25 — ns Figure 25.25
Single
edge
t
TMCWH
1.5 — 1.5 — t
cyc
Timer
clock
pulse
width
Both
edges
t
TMCWL
2.5 — 2.5 —
WDT0 Overflow output
delay time
t
WOVD
— 60 — 40 ns Figure 25.27
WDT1 Buzz output delay
time
t
BUZD
— 60 — 40 ns Figure 25.28
PWM Pulse output delay
time
t
PWOD
— 60 — 40 ns Figure 25.29
SCI Asynchro-
nous
t
Scyc
4 — 4 — t
cyc
Figure 25.30
Input
clock
cycle
Synchro-
nous
6 — 6 —
Input clock pulse
width
t
SCKW
0.4 0.6 0.4 0.6 t
Scyc
Input clock rise
time
t
SCKr
— 1.5 — 1.5 t
cyc
Input clock fall
time
t
SCKf
— 1.5 — 1.5
Transmit data
delay time
t
TXD
— 60 — 40 ns Figure 25.31
Receive data setup
time (synchronous)
t
RXS
60 — 40 —
Receive data hold
time (synchronous)
t
RXH
60 — 40 —
A/D
converter
Trigger input setup
time
t
TRGS
60 — 40 — ns Figure 25.32
Notes: 1. AV
CC
= 3.3 V to 5.5 V if A/D and D/A not used (pins used as I/O ports).
2. Vref = 3.3 V to AV
CC
if A/D and D/A not used (pins used as I/O ports).
3. Only available I/O port, TMR, WDT0, and WDT1.