Datasheet

Section 26 Electrical Characteristics
(H8S/2633R)
Page 1094 of 1434 R01UH0166EJ0600 Rev. 6.00
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
26.3.1 Clock Timing
Table 26.5 lists the clock timing
Table 26.5 Clock Timing
Conditions: PV
CC
= 4.5 V to 5.5 V, AV
CC
= 4.5 V to 5.5 V, V
ref
= 4.5 V to AV
CC
,
V
SS
= AV
SS
= PLLV
SS
= 0 V, φ = 32.768 kHz, 2 to 28 MHz
*
,
T
a
= –20°C to +75°C (regular specifications), T
a
= –40°C to +85°C (wide-range
specifications)
28MHz
Item Symbol Min Max Unit
Test
Conditions
Clock cycle time t
cyc
35.7 500 ns Figure 26.2
Clock high pulse width t
CH
10 — ns
Clock low pulse width t
CL
10 — ns
Clock rise time t
Cr
— 5 ns
Clock fall time t
Cf
— 5 ns
Clock oscillator settling
time at reset (crystal)
t
OSC1
10 — ms Figure 26.3
Clock oscillator settling time in
software standby (crystal)
t
OSC2
5 — ms Figure 24.3
External clock output stabilization
delay time
t
DEXT
2 — ms Figure 26.3
32 kHz clock oscillation settling time t
OSC3
— 2 s
Sub clock oscillator frequency f
SUB
32.768 32.768 kHz
Sub clock (φ
SUB
) cycle time t
SUB
30.5 30.5 μs
Note: * The input clock frequency should be set to 25 MHz or less. If φ = 25 MHz to 28 MHz, use
the PLL to multiply the frequency (×2 or ×4).