Datasheet

Section 26 Electrical Characteristics
(H8S/2633R)
Page 1098 of 1434 R01UH0166EJ0600 Rev. 6.00
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
26.3.3 Bus Timing
Table 26.7 lists the bus timing.
Table 26.7 Bus Timing
Conditions: PV
CC
= 4.5 V to 5.5 V, AV
CC
= 4.5 V to 5.5 V, V
ref
= 4.5 V to AV
CC
,
V
SS
= AV
SS
= PLLV
SS
= 0 V, φ = 2 to 28 MHz, T
a
= –20°C to +75°C (regular
specifications), T
a
= –40°C to +85°C (wide-range specifications)
Item Symbol Min Max Unit Test Conditions
Address delay time t
AD
— 20 ns
Address setup time t
AS
0.5 × t
cyc
– 13 — ns
Figure 26.6 to
figure 26.11
Address hold time t
AH
0.5 × t
cyc
– 8 — ns
CS delay time 1 t
CSD1
— 15 ns
CS delay time 2 t
CSD2
— 15 ns
AS delay time t
ASD
— 15 ns
RD delay time 1 t
RSD1
— 15 ns
RD delay time 2 t
RSD2
— 15 ns
Read data setup time t
RDS
15 — ns
Read data hold time t
RDH
0 — ns
Read data access time 1 t
ACC1
— 1.0 × t
cyc
– 15 ns
Read data access time 2 t
ACC2
— 1.5 × t
cyc
– 15 ns
Read data access time 3 t
ACC3
— 2.0 × t
cyc
– 15 ns
Read data access time 4 t
ACC4
— 2.5 × t
cyc
– 15 ns
Read data access time 5 t
ACC5
— 3.0 × t
cyc
– 15 ns
WR delay time 1 t
WRD1
— 15 ns
WR delay time 2 t
WRD2
— 15 ns
WR pulse width 1 t
WSW1
1.0 × t
cyc
– 13 — ns
WR pulse width 2 t
WSW2
1.5 × t
cyc
– 13 — ns
Write data delay time t
WDD
— 22 ns
Write data setup time t
WDS
0.5 × t
cyc
– 13 — ns
Write data hold time t
WDH
0.5 × t
cyc
– 8 — ns
WR setup time t
WCS
0.5 × t
cyc
– 10 — ns
WR hold time t
WCH
0.5 × t
cyc
– 10 — ns