Datasheet

Section 26 Electrical Characteristics
(H8S/2633R)
Page 1112 of 1434 R01UH0166EJ0600 Rev. 6.00
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
26.3.5 Timing of On-Chip Supporting Modules
Table 26.9 lists the timing of on-chip supporting modules.
Table 26.9 Timing of On-Chip Supporting Modules
Conditions: PV
CC
= 4.5 V to 5.5 V, AV
CC
= 4.5 V to 5.5 V, V
ref
= 4.5 V to AV
CC
,
V
SS
= AV
SS
= PLLV
SS
= 0 V, φ = 32.768 kHz
*
, 2 to 28 MHz,
T
a
= –20°C to +75°C (regular specifications), T
a
= –40°C to +85°C (wide-range
specifications)
Item Symbol Min Max Unit Test Conditions
I/O port Output data delay time t
PWD
— 40 ns Figure 26.20
Input data setup time t
PRS
25 —
Input data hold time t
PRH
25 —
PPG Pulse output delay time t
POD
— 40 ns Figure 26.21
TPU Timer output delay time t
TOCD
— 40 ns Figure 26.22
Timer input setup time t
TICS
25 —
Timer clock input setup time t
TCKS
25 — ns Figure 26.23
Single edge t
TCKWH
1.5 — t
cyc
Timer clock
pulse width
Both edges t
TCKWL
2.5 —
TMR Timer output delay time t
TMOD
— 40 ns Figure 26.24
Timer reset input setup time t
TMRS
25 — ns Figure 26.26
Timer clock input setup time t
TMCS
25 — ns Figure 26.25
Single edge t
TMCWH
1.5 — t
cyc
Timer clock
pulse width
Both edges t
TMCWL
2.5 —
WDT0 Overflow output delay time t
WOVD
— 40 ns Figure 26.27
WDT1 Buzz output delay time t
BUZD
— 40 ns Figure 26.28
PWM Pulse output delay time t
PWOD
— 40 ns Figure 26.29
SCI Asynchronous t
Scyc
4 — t
cyc
Figure 26.30
Input clock
cycle
Synchronous 6 —
Input clock pulse width t
SCKW
0.4 0.6 t
Scyc
Input clock rise time t
SCKr
— 1.5 t
cyc
Input clock fall time t
SCKf
— 1.5