Datasheet

Appendix A Instruction Set
R01UH0166EJ0600 Rev. 6.00 Page 1153 of 1434
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
Addressing Mode/
Instruction Length (Bytes)
Operand Size
#xx
Rn
@ERn
@(d,ERn)
@–ERn/@ERn+
@aa
@(d,PC)
@@aa
—
Mnemonic
EXTS TAS*
3
MAC CLRMAC LDMAC STMAC
EXTS.W Rd W 2 EXTS.L ERd L 2 TAS @ERd B 4 MAC @ERn+, @ERm+ 4 CLRMAC LDMAC ERs,MACH LDMAC ERs,MACL STMAC MACH,ERd STMAC MACL,ERd
(<bit 7> of Rd16)→ — — 0 — 1
(<bit 15 to 8> of Rd16) (<bit 15> of ERd32)→ — — 0 — 1 (<bit 31 to 16> of ERd32) @ERd-0→CCR set, (1)→ — — 0 — 4 (<bit 7> of @ERd)
@ERnx@ERm+MAC→MAC — — — — — — 4 (signal multiplication)
[11] [11] [11]
@ERn+2→ERn, ERm+2→ERm
0→MACH, MACL — — — — — — 2 [12] ERs→MACH — — — — — — 2 [12] ERs→MACL — — — — — — 2 [12] MACH→ERd — — — 1 [12]
MACL→ERd — — — 1 [12]
Operation
Condition Code
IHNZVC
Advanced
No. of States
*
1
↔ ↔ ↔
↔ ↔ ↔
↔
↔
↔
↔
↔
↔
— —
L L L L
2 2 2 2
2