Datasheet

Appendix A Instruction Set
R01UH0166EJ0600 Rev. 6.00 Page 1183 of 1434
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
XORC #xx:8,CCR XORC #xx:8,EXR
Mnemonic
Size
Instruction Format
1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte
Instruc-
tion
XORC B
B
0 0
5 1
4
1 0 5
IMM
IMM
Notes: 1.
2. 3.
Bit 7 of the 4th byte of the MOV.L ERs, @(d:32,ERd) instruction can be either 1 or 0. When using the TAS instruction, use register ER0, ER1, ER4, or ER5. Only register ER0 to ER6 should be used when using the STM/LDM instruction.
Legend:
Address Register 32-Bit Register
Register Field
General Register
Register Field
General Register
Register Field
General Register
000 001
• • •
111
ER0 ER1
• • •
ER7
0000 0001
• • •
0111 1000 1001
• • •
1111
R0 R1
• • •
R7
E0 E1
• • •
E7
0000 0001
• • •
0111 1000 1001
• • •
1111
R0H R1H
• • •
R7H
R0L R1L
• • •
R7L
16-Bit Register 8-Bit Register
IMM: abs: disp: rs, rd, rn: ers, erd, ern, erm: The register fields specify general registers as follows.
Immediate data (2, 3, 8, 16, or 32 bits) Absolute address (8, 16, 24, or 32 bits) Displacement (8, 16, or 32 bits) Register field (4 bits specifying an 8-bit or 16-bit register. The symbols rs, rd, and rn correspond to operand symbols Rs, Rd,and Rn.) Register field (3 bits specifying an address register or 32-bit register. The symbols ers, erd, ern, and erm correspond to operand symbols ERs, ERd, ERn, and ERm.)