Datasheet

Appendix A Instruction Set
R01UH0166EJ0600 Rev. 6.00 Page 1201 of 1434
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
Instruction
Fetch
Branch
Address
Read
Stack
Operation
Byte
Data
Access
Word
Data
Access
Internal
Operation
Instruction Mnemonic I J K L M N
XOR XOR.B #xx:8,Rd 1
XOR.B Rs,Rd 1
XOR.W #xx:16,Rd 2
XOR.W Rs,Rd 1
XOR.L #xx:32,ERd 3
XOR.L ERs,ERd 2
XORC XORC #xx:8,CCR 1
XORC #xx:8,EXR 2
Notes: 1. 2 when EXR is invalid, 3 when EXR is valid.
2. When n bytes of data are transferred.
3. An internal operation may require between 0 and 3 additional states, depending on the
preceding instruction.
4. When using the TAS instruction, use register ER0, ER1, ER4, or ER5.
5. Only register ER0 to ER6 should be used when using the STM/LDM instruction.