Datasheet

Section 2 CPU
R01UH0166EJ0600 Rev. 6.00 Page 71 of 1434
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
Type Instruction Size
*
1
Function
Arithmetic
operations
DAA
DAS
B Rd decimal adjust → Rd
Decimal-adjusts an addition or subtraction result in a
general register by referring to the CCR to produce 4-bit
BCD data.
MULXU B/W Rd × Rs → Rd
Performs unsigned multiplication on data in two general
registers: either 8 bits × 8 bits → 16 bits or 16 bits ×
16 bits → 32 bits.
MULXS B/W Rd × Rs → Rd
Performs signed multiplication on data in two general
registers: either 8 bits × 8 bits → 16 bits or 16 bits ×
16 bits → 32 bits.
DIVXU B/W Rd ÷ Rs → Rd
Performs unsigned division on data in two general
registers: either 16 bits ÷ 8 bits → 8-bit quotient and 8-bit
remainder or 32 bits ÷ 16 bits → 16-bit quotient and 16-
bit remainder.
DIVXS B/W Rd ÷ Rs → Rd
Performs signed division on data in two general
registers: either 16 bits ÷ 8 bits → 8-bit quotient and 8-bit
remainder or 32 bits ÷ 16 bits → 16-bit quotient and 16-
bit remainder.
CMP B/W/L Rd – Rs, Rd – #IMM
Compares data in a general register with data in another
general register or with immediate data, and sets CCR
bits according to the result.
NEG B/W/L 0 – Rd → Rd
Takes the two's complement (arithmetic complement) of
data in a general register.
EXTU W/L Rd (zero extension) → Rd
Extends the lower 8 bits of a 16-bit register to word size,
or the lower 16 bits of a 32-bit register to longword size,
by padding with zeros on the left.
EXTS W/L Rd (sign extension) → Rd
Extends the lower 8 bits of a 16-bit register to word size,
or the lower 16 bits of a 32-bit register to longword size,
by extending the sign bit.
TAS
*
3
B @ERd – 0, 1 → (<bit 7> of @Erd)
Tests memory contents, and sets the most significant bit
(bit 7) to 1.