Datasheet

Appendix A Instruction Set
R01UH0166EJ0600 Rev. 6.00 Page 1215 of 1434
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
Instruction
Reset exception handling
R:W VEC R:W VEC+2
Internal operation,
R:W
*
5
1 state
Interrupt exception handling
R:W
*
6
Internal operation,
W:W stack (L) W:W stack (H)
W:W stack (EXR)
R:W:M VEC R:W VEC+2
Internal operation,
R:W
*
7
1 state
1 state
Notes: 1. EAs is the contents of ER5. EAd is the contents of ER6. 2. EAs is the contents of ER5. EAd is the contents of ER6. Both registers are incremented by 1 after execution of the instruction. n is the initial value of R4L or R4. If n = 0, these bus cycles are not executed. 3. Repeated two times to save or restore two registers, three times for three registers, or four times for four registers. 4. Start address after return. 5. Start address of the program. 6. Prefetch address, equal to two plus the PC value pushed onto the stack. In recovery from sleep mode or software standby mode the read operation is replaced by an internal operation. 7. Start address of the interrupt-handling routine. 8. When using the TAS instruction, use register ER0, ER1, ER4, or ER5. 9. Only register ER0 to ER6 should be used when using the STM/LDM instruction.
1 2 3 4 5 6 7 8 9