Datasheet

Section 2 CPU
Page 72 of 1434 R01UH0166EJ0600 Rev. 6.00
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
Type Instruction Size
*
1
Function
Arithmetic
operations
MAC — (EAs) × (EAd) + MAC → MAC
Performs signed multiplication on memory contents and
adds the result to the multiply-accumulate register. The
following operations can be performed:
16 bits × 16 bits + 32 bits → 32 bits, saturating
16 bits × 16 bits + 42 bits → 42 bits, non-saturating
CLRMAC — 0 → MAC
Clears the multiply-accumulate register to zero.
LDMAC
STMAC
L Rs → MAC, MAC → Rd
Transfers data between a general register and a
multiply-accumulate register.
Logic
operations
AND B/W/L Rd ∧ Rs → Rd, Rd ∧ #IMM → Rd
Performs a logical AND operation on a general register
and another general register or immediate data.
OR B/W/L Rd ∨ Rs → Rd, Rd ∨ #IMM → Rd
Performs a logical OR operation on a general register
and another general register or immediate data.
XOR B/W/L Rd ⊕ Rs → Rd, Rd ⊕ #IMM → Rd
Performs a logical exclusive OR operation on a general
register and another general register or immediate data.
NOT B/W/L ¬ (Rd) → (Rd)
Takes the one's complement of general register
contents.
Shift
operations
SHAL
SHAR
B/W/L Rd (shift) → Rd
Performs an arithmetic shift on general register contents.
1-bit or 2-bit shift is possible.
SHLL
SHLR
B/W/L Rd (shift) → Rd
Performs a logical shift on general register contents.
1-bit or 2-bit shift is possible.
ROTL
ROTR
B/W/L Rd (rotate) → Rd
Rotates general register contents.
1-bit or 2-bit rotation is possible.
ROTXL
ROTXR
B/W/L Rd (rotate) → Rd
Rotates general register contents through the carry flag.
1-bit or 2-bit rotation is possible.