Datasheet

Appendix B Internal I/O Register
Page 1240 of 1434 R01UH0166EJ0600 Rev. 6.00
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
IrCR—IrDA Control Register H'FDB0 SCI0, IrDA
7
IrE
0
R/W
6
IrCKS2
0
R/W
5
IrCKS1
0
R/W
4
IrCKS0
0
R/W
3
—
0
—
0
—
0
—
2
—
0
—
1
—
0
—
IrDA enable
0 TxD0/IrTxD and RxD0/IrRxD pins function as TxD0 and RxD0.
1 TxD0/IrTxD and RxD0/IrRxD pins function as IrTx0 and IrRxD.
IrDA clock select 2 to 0
Bit 6 Bit 5 Bit 4 Description
IrCKS2 IrCKS1 IrCKS0
0 0 0 B × 3/16 (3/16ths of bit rate)
1 φ/2
1 0 φ/4
1 φ/8
1 0 0 φ/16
1 φ/32
1 0 φ/64
1 φ/128
Bit
Initial value
R/W
:
:
:
SCRX—Serial Control Register X H'FDB4 IIC
7
—
0
R/W
6
IICX1
0
R/W
5
IICX0
0
R/W
4
IICE
0
R/W
3
FLSHE
0
R/W
0
—
0
R/W
2
—
0
R/W
1
—
0
R/W
I
2
C transfer rate select 1, 0
Selects the transfer rate in master mode in conjunction with CKS2 to CKS0 in ICMR.
See the section on the I
2
C bus mode register (ICMR) for details.
I
2
C master enable
0 Disables CPU access of
I
2
C
bus interface data register and control
register.
1 Enables CPU access of
I
2
C
bus interface data register and control
register.
Flash memory control register enable
Bit
Initial value
R/W
:
:
:
0
1
Excludes addresses H'FFFFA8 to H'FFFFAC as flash control
registers. (Initial value)
Selects addresses H'FFFFA8 to H'FFFFAC as flash control
registers.