Datasheet

Appendix B Internal I/O Register
R01UH0166EJ0600 Rev. 6.00 Page 1241 of 1434
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
DDCSWR—DDC Switch Register H'FDB5 IIC
7
—
0
R/(W)
*
1
6
—
0
R/(W)
*
1
5
—
0
R/(W)
*
1
4
—
0
R/(W)
*
1
3
CLR3
1
W
*
2
0
CLR0
1
W
*
2
2
CLR2
1
W
*
2
1
CLR1
1
W
*
2
Notes: 1. Should always be written with 0.
2. Always read as 1.
Reserved bit
Bit
Initial value
R/W
:
:
:
IIC clear 3 to 0
CLR3 CLR2 CLR1 CLR0
0 0 — —
1 0 0
1
1 0
1
1 — — —
Setting prohibited
Setting prohibited
IIC0 internal latch cleared
IIC1 internal latch cleared
IIC0 and IIC1 internal latch cleared
Invalid setting