Datasheet

Appendix B Internal I/O Register
Page 1242 of 1434 R01UH0166EJ0600 Rev. 6.00
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
DACR0—PWM (D/A) Control Register 0
DACR1—PWM (D/A) Control Register 1
H'FDB8
H'FDBC
PWM0
PWM1
7
TEST
0
R/W
6
PWME
0
R/W
5
—
1
—
4
—
1
—
3
OEB
0
R/W
0
CKS
0
R/W
2
OEA
0
R/W
1
OS
0
R/W
Test mode
0 PWM (D/A) in user status and operating normally.
1 PWM (D/A) in test status and will not return correct result of conversion.
PWM enable
0 DACNT operates as 14-bit up-counter.
1 Count stops when DACNT = H'0003.
Output enable B
0 PWM (D/A) channel B output (PWM1/PWM3 output pin) disabled.
1 PWM (D/A) channel B output (PWM1/PWM3 output pin) enabled.
Output enable A
0 PWM (D/A) channel A output (PWM0/PWM2 output pin) disabled.
1 PWM (D/A) channel A output (PWM0/PWM2 output pin) enabled.
Output select
0 Direct PWM output.
1 Inverted PWM output.
Clock select
0 Resolution (T) = system clock cycle (tcyc).
1 Resolution (T) = system clock cycle (tcyc) × 2.
Bit
Initial value
R/W
:
:
: