Datasheet

Appendix B Internal I/O Register
R01UH0166EJ0600 Rev. 6.00 Page 1243 of 1434
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
DADRAH0—PWM (D/A) Data Register AH0
DADRAL0—PWM (D/A) Data Register AL0
DADRBH0—PWM (D/A) Data Register BH0
DADRBL0—PWM (D/A) Data Register BL0
DADRAH1—PWM (D/A) Data Register AH1
DADRAL1—PWM (D/A) Data Register AL1
DADRBH1—PWM (D/A) Data Register BH1
DADRBL1—PWM (D/A) Data Register BL1
H'FDB8
H'FDB9
H'FDBA
H'FDBB
H'FDBC
H'FDBD
H'FDBE
H'FDBF
PWM0
PWM0
PWM0
PWM0
PWM1
PWM1
PWM1
PWM1
15
13
DA13
1
R/W
14
12
DA12
1
R/W
13
11
DA11
1
R/W
12
10
DA10
1
R/W
11
9
DA9
1
R/W
8
6
DA6
1
R/W
10
8
DA8
1
R/W
9
7
DA7
1
R/W
7
5
DA5
1
R/W
6
4
DA4
1
R/W
5
3
DA3
1
R/W
4
2
DA2
1
R/W
3
1
DA1
1
R/W
0
—
—
1
—
2
0
DA0
1
R/W
1
—
CFS
1
R/W
DADRH
DADRL
DA13
1
R/W
DA12
1
R/W
DA11
1
R/W
DA10
1
R/W
DA9
1
R/W
DA6
1
R/W
DA8
1
R/W
DA7
1
R/W
DA5
1
R/W
DA4
1
R/W
DA3
1
R/W
DA2
1
R/W
DA1
1
R/W
REGS
1
R/W
DA0
1
R/W
CFS
1
R/W
Carrier frequency select
0 Basic cycle = resolution (T) × 64. DADR range = H'0401 to H'FFFD
1 Basic cycle = resolution (T) ×256. DADR range = H'0103 to H'FFFF
Carrier frequency select
0 Basic cycle = resolution (T) × 64. DADR range = H'0401 to H'FFFD
1 Basic cycle = resolution (T) × 256. DADR range = H'0103 to H'FFFF
Register select
0 DADRA and DADRB access enabled.
1 DACR and DACNT access enabled.
D/A data 13 to 0
D/A data 13 to 0
Bit (CPU)
Bit (Data)
DADRA
Initial value
R/W
:
:
:
:
DADRB
Initial value
R/W
:
:
: