Datasheet
Appendix B Internal I/O Register
Page 1248 of 1434 R01UH0166EJ0600 Rev. 6.00
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
SMR3—Serial Mode Register 3
SMR4—Serial Mode Register 4
SMR0—Serial Mode Register 0
SMR1—Serial Mode Register 1
SMR2—Serial Mode Register 2
H'FDD0
H'FDD8
H'FF78
H'FF80
H'FF88
SCI3
SCI4
SCI0
SCI1
SCI2
7
C/A
0
R/W
6
CHR
0
R/W
5
PE
0
R/W
4
O/E
0
R/W
3
STOP
0
R/W
0
CKS0
0
R/W
2
MP
0
R/W
1
CKS1
0
R/W
Communication mode
0 Asynchronous mode
1 Clocked synchronous mode
Parity enable
0 Parity bit addition and checking disabled
1 Parity bit addition and checking enabled*
Stop bit length
0 1 stop bit: In transmission, a single 1 bit (stop bit) is added to the
end of a transmit character before it is sent.
1 2 stop bits: In transmission, two 1 bits (stop bits) are added to the
end of a transmit character before it is sent.
Parity mode
0 Even parity
*
1
1 Odd parity
*
2
Clock select 1 and 0
CKS1 CKS0 Description
0 0 φ clock
1 φ/4 clock
1 0 φ/16 clock
1 φ/64 clock
Bit
Initial value
R/W
:
:
:
Multiprocessor mode
Multiprocessor function disabled
Multiprocessor format selected
0
1
Notes: 1. When even parity is set, parity bit addition is performed in transmission
so that the total number of 1 bits in the transmit character plus the parity
bit is even.
In reception, a check is performed to see if the total number of 1 bits in
the receive character plus the parity bit is even.
2. When odd parity is set, parity bit addition is performed in transmission
so that the total number of 1 bits in the transmit character plus the
parity bit is odd.
In reception, a check is performed to see if the total number of 1 bits in
the receive character plus the parity bit is odd.
Note: * When the PE bit is set to 1, the parity (even or odd) specified by the O/E bit is
added to transmit data before transmission. In reception, the parity bit is checked
for the parity (even or odd) specified by the O/E bit.
Character length
0 8-bit data
1 7-bit data*
Note: * When 7-bit data is selected, the MSB (bit 7) of TDR is not transmitted, and
it is not possible to choose between LSB-first or MSB-first transfer.