Datasheet

Appendix B Internal I/O Register
R01UH0166EJ0600 Rev. 6.00 Page 1253 of 1434
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
SSR3—Serial Status Register 3
SSR4—Serial Status Register 4
SSR0—Serial Status Register 0
SSR1—Serial Status Register 1
SSR2—Serial Status Register 2
H'FDD4
H'FDDC
H'FF7C
H'FF84
H'FF8C
SCI3
SCI4
SCI0
SCI1
SCI2
7
TDRE
1
R/(W)*
1
6
RDRF
0
R/(W)*
1
5
ORER
0
R/(W)*
1
4
FER
0
R/(W)*
1
3
PER
0
R/(W)*
1
0
MPBT
0
R/W
2
TEND
1
R
1
MPB
0
R
Multiprocessor bit transfer (MPBT)
Bit
Initial value
R/W
:
:
:
0
1
Transfer data “multiprocessor bit = 0”. (initial value)
Transfer data “multiprocessor bit = 1”.
Multiprocessor bit (MPB)
0
1
[Clearing condition] (initial value)
*
2
When data “multiprocessor bit = 0” is received.
[Setting condition]
When data “multiprocessor bit = 1” is received.
Overrun error (ORER)
0
1
[Clearing condition]
(initial value)
*
8
Writing 0 to ORER after reading ORER=1.
[Setting condition]
On completion of next serial receive operation when RDRF=1.
*
9
Transmit data register empty (TDRE)
0
1
[Clearing conditions]
(1) Writing 0 to TDRE after reading TDRE=1;
(2) When data written to TDR by DMAC
*
3
or DTC
*
3
by TXI interrupt request;
[Setting conditions] (initial value)
(1) When SCR TE bit=0;
(2) When data is sent from TDR to TSR and data can be written to TDR.
Receive data register full (RDRF)
*
10
0
1
[Clearing conditions] (initial value)
(1) Writing 0 to RDRF after reading RDRF=1.
(2) After reading RDR data by DMAC
*
3
or DTC
*
3
by RXI interrupt request.
[Setting condition]
When receive data is sent from RSR to RDR on normal completion of serial receive operation.
Framing error (FER)
0
1
[Clearing condition] (initial value)
*
6
Writing 0 to FER after reading FER=1.
[Setting condition]
When SCI checks if the stop bit at the end of receive data is 1 on completion of receiving, the stop bit is found to be 0.
*
7
Parity error (PER)
0
1
[Clearing condition] (initial value)
*
4
Writing 0 to PER after reading PER=1;
[Setting condition]
When receiving, when the number of 1s in receive data plus parity bit does not match the even or odd
parity specified in the SMR O/E bit.
*
5
Transmit end (TEND)
0
1
[Clearing conditions]
(1) Writing 0 to TDRE flag after reading TDRE=1;
(2) When data is written to TDR by DMAC
*
3
or DTC
*
3
by TXI interrupt request.
[Setting conditions] (initial value)
(1) When SCR TE bit=0;
(2) When TDRE=1 at transfer of last bit of any byte of serial transmit character.
Notes:
1. Only 0 can be written to these bits (to clear these flags).
2. The existing status is continued when, in multi-processor format, the SCR RE bit is cleared to 0.
3. This function is not available in the H8S/2695.
4. The PER flag is not affected and retains its previous state when the RE bit in SCR is cleared to 0.
5. If a parity error occurs, the receive data is transferred to RDR but the RDRF flag is not set. Also, subsequent serial reception cannot be continued while the PER
flag is set to 1. In clocked synchronous mode, serial transmission cannot be continued, either.
6. The FER flag is not affected and retains its previous state when the RE bit in SCR is cleared to 0.
7. In 2-stop-bit mode, only the first stop bit is checked for a value of 0; the second stop bit is not checked. If a framing error occurs, the receive data is transferred to
RDR but the RDRF flag is not set. Also, subsequent serial reception cannot be continued while the FER flag is set to 1. In clocked synchronous mode, serial
transmission cannot be continued, either.
8. The ORER flag is not affected and retains its previous state when the RE bit in SCR is cleared to 0.
9. The receive data prior to the overrun error is retained in RDR, and the data received subsequently is lost. Also, subsequent serial reception cannot be continued
while the ORER flag is set to 1. In clocked synchronous mode, serial transmission cannot be continued, either.
10. RDR and the RDRF flag are not affected and retain their previous values when an error is detected during reception or when the RE bit in SCR is cleared to 0.
If reception of the next data is completed while the RDRF flag is still set to 1, an overrun error will occur and the receive data will be lost.