Datasheet

Appendix B Internal I/O Register
Page 1256 of 1434 R01UH0166EJ0600 Rev. 6.00
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
SYSCR—System Control Register H'FDE5 System
7
MACS
0
R/W
6
—
0
—
5
INTM1
0
R/W
4
INTM0
0
R/W
3
NMIEG
0
R/W
0
RAME
1
R/W
2
MRESE
0
R/W
1
—
0
—
0
MAC saturation
Manual reset disabled.
Pins P74/TMO2/MRES can be used as P74/TMO2 I/O pins.
Manual reset enabled.
Pins P74/TMO2/MRES can be used as MRES input pins.
1
Non-saturating calculation for MAC instruction
Saturating calculation for MAC instruction
0
1
Interrupt control mode 1, 0
Interrupt request issued on falling edge of NMI input.
Interrupt request issued on rising edge of NMI input.
0
1
Internal RAM disabled.
Internal RAM enabled.
0
1
NMI edge select
RAM Enable
Manual reset select bit
00 0 Interrupt controlled by bit I
INTM0INTM1
Interrupt
control mode
1 — Do not set.
01 2 Interrupt controlled by bits I2 to I0 and IPR.
1 — Do not set.
Bit
Initial value
R/W
:
:
: